Hello, I'm Youngho.
I want to know power sequencing of MPC8548E.
According to its datasheet, MPC8548EEC, power sequencing is just 2 steps as follows:
1. V_DD, AV_DD_n, BV_DD, LV_DD, OV_DD, SV_DD, TV_DD, XV_DD.
2. GV_DD.
And, the NOTE is as follows:
Note1: Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs.
Note 2: In order to guarantee MCKE low during power-up, the above sequencing for GV_DD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power-up, then the sequencing for GVDD is not required.
Note 3: From a system standpoint, if any of the I/O Power supplies ramp prior to the V_DD core supply, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device.
As I understood above, power sequencing is that the core powers is first powered up and then the I/O powers is next.
So, power sequencing I thought is as follows:
1.V_DD
2.AV_DD_n, SV_DD, XV_DD
3.BV_DD, OV_DD, LV_DD, TV_DD
4.GV_DD
Am I right?
