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The manual says that for case when L2 cache is configured as Memory-Mapped SRAM. Notice initialization should be made by software. So software designer decides how to initialize this memory.
* One way is execute software routine which fills this SRAM memory by the store instructions, i.e. initialize by core. Because in this case memory filled by sub-cache line transactions false ECC errors will be generated during the read-modify-write process. So software designer has to disable ECC error checking.
* The second way is programming DMA engine to write to this SRAM. For example we can move aligned cache-line size pattern from some memory to the SRAM. (For example we can move it from the NOR flash). In this case DMA engine uses cache-line writes; hence ECC checking can remain enabled during the initialization process.
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