1588 timer status register updating issue in P1021 rdb board

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1588 timer status register updating issue in P1021 rdb board

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Contributor III

Hi All,

We are working P1021 rdb, we need to measure the external clock frequency, for doing this using 1588 timer by selecting external clock as timer reference clock, we are able to read the clock frequency properly, but we are facing below issue..

Time stamp status register * (eTSEC1x_TMR_STAT) register has RCD bit to indicate the reference clock status. As per datasheet this bit values are described as below ( P1021 reference manual page number 1056 )..

0 ----> Selected timer reference clock is not active. User cannot access timer clock domain registers. Reads return 0; writes are ignored.

1 -----> Selected timer reference clock is active

Problem is, that RCD bit is updating only after a timer soft reset. I mean to say that  if there is a clock detected after a reset then RCD bit is set to 1, after that if you remove the clock then also bit is still 1, which has to be set to 0. Could you please let us know how to fix this issue, and for your information we are not using this 1588 timer for ethernet controller..vladcentea jimtrudeau

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NXP TechSupport
NXP TechSupport

This bit is updated after timer soft reset.


Have a great day,
Pavel Chubakov

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