VDDHIGH_IN supply for i.MX6Q

[teikhooiteoh]

Hi,

Does VDDHIGH_IN input supply for i.MX6Q required to be monotonic during rise time?

Any specifications on that?

In my design, VDDHIGH_IN is supplied by PMIC MMPF0100ANES VGEN5 (2.8V).

With just connection to the i.MX6Q input supply, a dip during the VDDHIGH_IN is observed.

Is this expected behavior?

[reyes]

Hi,

Doing a little further investigation, I found that the dip you are seen appears in the very beginning of the voltage power-on ramp-up curve, so it affects neither the power-up sequence nor further device operation.

You can find more details in the following link: https://community.nxp.com/message/805891

Have a great day,
Jose

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[teikhooiteoh]

Hi Jose,

Is there any possible reason for this? VDDHIGH_IN only connected almost

directly from PMIC VGEN5 output to i.MX6 input.

I did observed that if measure on the VCC_VG5_2V8 output alone (isolating

by removing R706), there is no such dip during rising.

Regards,

TEOH TEIK HOOI 张泽晖 | Staff Engineer | Electrical Engineering, Medical

R&D Division | Olympus Singapore Pte Ltd

Phone: (65) 6777 8978 | DID: (65) 6870 2585 | Mobile:(65) 9459 7235 | Fax:

(65) 6870 2508 | Email: teikhooi.teoh@olympus-ap.com

[reyes]

Hi TEOH TEIK HOOI,

The dip is caused by a current demand during the power-up sequence that VGEN5 cannot provide.

VDDHIGH was placed on VGEN5 early in the design as a compromise solution for a board designed primarily for software development. Validation of the i.MX6 processor has shown that operations at elevated temperatures may cause VDDHIGH_IN to require much more current than VGEN5 can supply. It is recommended for robust designs potentially operating at more extreme temperatures for VDDHIGH to be supplied from a power rail that can supply 250 mA or more.

This allows for datasheet maximum of 125 mA for internal VDDHIGH_IN loads plus 125 mA for external PHY IO loads.

Check Page 20 of the i.MX6Quad SABRE reference design that you can download from the following link: https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/sabre-development-...

In the i.MX6Quad SABRE design, you will find an optional LDO (U9) that could be reconfigured to supply both VDDHIGH_IN and VDD_SNVS_IN loads to meet the additional current requirements.

Thanks,

Jose

[reyes]

Hi,

According to the Hardware development guide for i.MX 6Q, VDDHIGH_IN should be the second in the power-up sequence and is typically supplied by SW2 of the PMIC: https://www.nxp.com/docs/en/user-guide/IMX6DQ6SDLHDG.pdf

Probably this behavior is caused due to the sequence used in your application.

Have a great day,
Jose

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