Some questions about PF8100/PF8200 's Fault detection

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Some questions about PF8100/PF8200 's Fault detection

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k23428
Contributor I

1. On page 33:

捕获.PNG

How to understand "the fault condition is cleard"?

For example, if SW1 shutdown due to OV fault, I suppose that user clears the SW1_OV_S bit by I2C means clear the fault condition. Am I right?

2. On page 33~34:

捕获.PNG

A) How can processor reset the counter value ? I found the FAULT_CNT[3:0] is Read only.2.PNG

B) Again, how to understand "the faults have been cleared ?"

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guoweisun
NXP TechSupport
NXP TechSupport

1: fault condition clear means the fault condition disappear not  clear the fault bit.

2:FAULT_CNT[3:0] can be read and write I test it in EVB.

3:Same answer with questions1.

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