Hi Shailendra,
Do you have a logic analyzer or an oscilloscope to see what is going on the bus and double check the proper format/timing?
Note that the FS65 uses the ‘Mode 1′ SPI protocol, which means that the base value of the SCLK signal is zero (CPOL = 0), data are sampled on a falling edge and changed on a rising edge (CPHA = 1).

Best regards,
Tomas