Hello,
I am currently working with the FS2613D, together with the S32k358 BMS board. I am using Matlab design tool box for programming and I am having problems leaving the debug mode.
For the SPI communication, I confirmed that the MCU is in INIT_FS state by reading from the FS_STATE register. It shows 01001 at bit 4-0. I also checked the FS_DIAG_SFATY register to confirm that the ABIST1 is marked as Pass and LBIST is marked as OK.
After, I read the watchdog token from FS_WD_TOKEN[0x5ab2] and wrote the processed data into FS_WD_ANSWER. At this state, i should have closed the INIT_FS state. After reading and writting to the watchdog, the BMS starts to blinking red and green led at the same not but not the orange led, it appears to be restarting the program continuously.
After i added the line to request to leave debug mode by writting into FS_STATES and request to release FS0B and FS1B by reading wd token and write into the FS_RELEASE_FS0B_FS1B, the BMS board starts to blinking red, green and orange led. which i am assuming that the FS26 is restarting the bms by continously resetting the power.
I am confused about why is this happening. I am currently suspecting it is related to the watchdog refresh. Reading from the FS_WDW_DURATION, the watch dog open window is about 3 ms, and the close:open is 50%:50%. I am calling a function every 3ms after the first watchdog write. The first call is skipped because the first half is the closed window, and the second call is made at the next 3ms to read and write the proper watchdog token. Is there anything wrong about this operation? I am a bit confused about the watchdog timing. When a good watchdog refresh is written into the register, does it immediately opens a new window? If so, since i am using 50% closed window, then i will have to write within 3ms after 3ms has passed since the previous write. Am i understanding it correctly?
The second thing that i am suspecting, is the device status returned. it returned 1100 0010. It seems that it indicates an event at FS_REG_FLG. When i checked into the register, it says a "Vbst over-voltage". I couldn't clear the bit by writting a 1 into the position. But i do notice that this VBST is responsible for the buck-boost operation which is reasonable to recieve a overvoltage flag continousely. Is it also a problem that is stopping me from leaving debug mode and release FS0B and FS1B, considering the device should have no error reporting?
Please let me know if there is anything that i did wrong or if i am missing anything. Thank you very much.
Hello,
First of all, please check if the FS26 is in Debug mode or not.
In Debug mode, the INIT FS window (256ms) is infinite and the WD window is fully opened meaning WD timing errors are not taken into account (the watchdog error counter will not be incremented).
In non-Debug mode, the first WD refresh must happen before INIT_FS timeout (256ms), the second and other should happen in the WD open window what is more restrictive.
The WD window duty cycle is configurable using WDW_DC[2:0] and by default is set to 50%.
The Watchdog impact on RSTB is configurable using WD_FS_REACTION [1:0] bits. By default (0b10) both RSTB and FS0B are asserted low if WD Error counter value = WD_ERR_LIMIT[1:0].
BRs, Tomas
Thank you very much for your reply.
Based on the register data, my FS26 is in debug mode, Init_FS state. I wish to leave the debug mode. According to the datasheet, i need a good wd refresh to leave the debug mode and continousely make watchdog refresh to clear the flt_err_cnt, even though i disable the watchdog window by setting it to zero. I checked with the sample token and corresponding answer, my calculations seemed to be correct. However, whenever i write the answer to the register, the MCU restarts because i can see the leds are blinking. I can't monitor the internal variable value for the mcu is restarting itself. Is it a sign of bad watchdog refresh or error in answer calculation?
Hello,
As shown before, to leave the Debug mode, write DBG_EXIT bit = ‘1’ in FS_STATES register. For more information, please refer to our AN13850 - NXP FS26 Implementation and Behaviors. This AN is classified as a secure file requiring an NDA:
BRs, Tomas