PF8100 - Accuracy and efficency in PFM and PFM mode

[bernhardfink]

Customer:    SICK (Germany)

Platform:      i.MX 8M Mini

SICK uses the PF8100 in their product to support the i.MX 8MM as well as an external FPGA.

They have seen in the PMIC data sheet that the tolerance of the voltage is given with +/- 2% for PWM mode and this would be ok for the requirements of the PCIe implementation in the FPGA.

In PFM mode the tolerance is given as an absolute mV number and here the requirements for the FPGA PCIe is not met.

Can we confirm that this it like it is?

They have seen as well the term "Auto Skip mode", which doesn't seem to be further explained.

Can you give some explanation for this mode?

Goal for SICK is a power effcient implementation of the buck regulator for this FPGA domain, because the majority of the time this domain is in a low current mode, so efficiency in this power state is important.

Regards,

Bernhard.

[reyes]

Hi Bernhand,

For your first question, I have requested assistance from the Applications teams, I personally think that ‘this is like it is’ and what is given in the document would be the tolerance, but, I want to double check with the apps team before giving an answer to the customer. I’ll get back on this as soon as I receive an update from them.

About the second question, In "Auto Skip mode" mode, the regulator moves automatically between pulse skipping mode and PWM mode depending on load conditions.

This mode offers a good compromise between PFM and PWM operation. At light load currents it offers higher efficiency than PWM mode, but in most cases, lower efficiency than PFM mode. At higher load currents, switching automatically transitions to PWM mode.

In the Auto skip mode, the top MOSFET is turned on for a fixed on time whenever output voltage falls below the reference voltage. A circuit monitors the inductor current and whenever it detects negative inductor current, the bottom MOSFET is turned off thus preventing discharge of the output capacitor.

If the output voltage goes above the reference voltage and remains so during the next clock cycle, the switching pulses are skipped, thus preventing switching and gate drive losses. When the circuit does not detect zero-crossing of the inductor in consecutive cycles, switching automatically transitions to PWM.

Regards,

Jose

NXP Semiconductors

[reyes]

Hi Bernhand,

I received an update from the Apps team about your first question, they told me that PF82/81 SW PFM mode output voltage accuracy is not as good as PWM mode. PFM mode is better than PWM mode on efficiency under low load current condition.

So, if FPGA enters low power mode, whether FPGA need the voltage accuracy requirement as same as normal work mode? 

Regards,

Jose

NXP Semiconductors

[bernhardfink]

Hi Jose,

I don't have enough knowledge about this product platform, maybe the FPGA is the master for the PCIe transactions and in this case it would be difficult to tell the i.MX 8M Plus upfront to switch back to PWM mode.

Further feedback from customer:

I understand that Pulse-Skipping is closely related to PWM and allows to improve efficiency at light loads by a reduction of switching activity.
One question remains, how does auto-skip mode affect accuracy? Or is it identical to the PWM accuracy given in the datasheet?

Additional question:
Is accuracy for the Bucks/LDOs even better if we only look at e.g. -10 °C to +85°C ?

Regards,

Bernhard.

[reyes]

Hi Bernhand,

Auto-skip mode accuracy is identical to the PWM accuracy given in the datasheet when working on PWM condition, the only difference is that using this Auto-skip mode, the PMIC is capable of detect low load current condition to change from PWM to PFM mode to improve accuracy on low loads.

The parameters indicated on the datasheet, including the accuracy for the Bucks/LDOs, are specified for all the temperature range from -40 to +105C. It will not be better on a reduced range like -10 to +85C.

Regards,

Jose

NXP Semiconductors