ONKEY_PUSHI interrupt in PF1510

cancel
Showing results for 
Search instead for 
Did you mean: 

ONKEY_PUSHI interrupt in PF1510

153 Views
Contributor I

Hi,

I have a question regarding ONKEY_PUSHI interrupt in PF1510.

The p.9.6 of datasheet states:

         "...The interrupt is generated during the rising edge of the ONKEY pin....",

then in Table 73. Register ONKEY_INT_STAT0 - ADDR 0x24, for bit 0:

         "Interrupt occurs whenever ONKEY button is pushed low for longer than the falling edge debounce setting. Interrupt also occurs whenever ONKEY button is released high for longer than the rising edge debounce setting, provided it went past the falling edge debounce time. In other words, this interrupt occurs whenever a change in status of the ONKEY_PUSHS sense bit occurs."

I have disabled RESET on ONKEY (0x00 in reg 0x59) and tried several times. It seems that interrupt for the bit 0 of reg 0x24 acts differently from other bits. When pressing ONKEY for a long time all bits, except bit 0, generate interrupt on both edges (falling & rising). Only bit 0 works only on rising edge, that is - it does not generate interrupt when button is pressed "low", only when going high. 

This is in contrary to the datasheet and is misleading. Could someone check it and clarify please?

Labels (2)
Tags (1)
0 Kudos
3 Replies

96 Views
Contributor I

Jose,

I have tested it again and:

a) reading ONKEY_INT_STAT0 does not clear it, or at least using simple i2c read/write (not PMIC driver) so I can see exactly which interrupt was triggered; 

b) try scenario: clearing ONKEY_INT_STAT0, setting PWRCTRL1 to 0x00, setting ONKEY_INT_MASK0 to 0x3E, push ONKEY and hold

- the ONKEY_INT_SENSE0 shows button pressed

- the ONKEY_INT_STAT0  does not show  that interrupt on bit '0' is triggered

- the INTB pin is not going low

c) release ONKEY

- the ONKEY_INT_SENSE0 shows button de-pressed

- the ONKEY_INT_STAT0  shows  that interrupt on bit '0' is triggered

- the INTB pin is going low

It seems that datasheet is not really clear about it or I am missing something. Anyway - it's not critical and we have made a workaround for that.

 

0 Kudos

119 Views
NXP TechSupport
NXP TechSupport

Hi,

ONKEY is an input pin to the IC and is typically connected to a push-button switch. The ONKEY pin is pulled high when the switch is depressed, and is pulled low when the switch is pressed. Pressing the switch generates interrupts which the processor uses to initiate PMIC state transitions

 

Reading ONKEY_PUSHI of register 0x24 clears the bit. I would rather recommend you to read ONKEY_INT bit on register 0x06. This bit is set high if any of the interrupts associated with ONKEY push button are set.

Or you can read the ONKEY_PUSHS bit, if ‘1’ then it means that ONKEY is pushed low. This follows the ONKEY button after the debounce circuit (debounce is programmable).

 

Make sure ONKEY_PUSHM bit is ‘0’, with this configuration, the Mask is removed and INTB pin is pulled low if corresponding interrupt status bit is set. By default, this bit is ‘1’(Mask enabled. INTB pin is not pulled low if corresponding interrupt status bit is set).

Regards,

Jose

0 Kudos

64 Views
Contributor I

Jose,

I have tested it again and:

a) reading ONKEY_INT_STAT0 does not clear it, or at least using simple i2c read/write (not PMIC driver) so I can see exactly which interrupt was triggered; 

b) try scenario: clearing ONKEY_INT_STAT0, setting PWRCTRL1 to 0x00, setting ONKEY_INT_MASK0 to 0x3E, push ONKEY and hold

- the ONKEY_INT_SENSE0 shows button pressed

- the ONKEY_INT_STAT0  does not show  that interrupt on bit '0' is triggered

- the INTB pin is not going low

c) release ONKEY

- the ONKEY_INT_SENSE0 shows button de-pressed

- the ONKEY_INT_STAT0  shows  that interrupt on bit '0' is triggered

- the INTB pin is going low

It seems that datasheet is not really clear about it or I am missing something. Anyway - it's not critical and we have made a workaround for that.

0 Kudos