Customer: PPC AG (Germany)
Platform: i.MX 8M Mini + PC9450A
Customer works with the Boundary Scan machine from Goepel to test their PCB in production. As part of this test they need to address the PMIC over the I2C bus. They also tested the level shifter in the PCA9450 and this is what they see:
I toggled the pins of the PMIC I2C level translator (PCA9450AHN) with boundary scan from the "low" side (1,8V) and measured voltages on the "high" side (3,3V).
During the test I observed the following behavior:
SDAL and SCLL are high (1,8V) => SDAL and SCLL are high = 3,1V => OK
SDAL is high (1,8V) SCLL is low (0 V) => SDAH = 2,4 V
and
SCLH is low = 0V => I expected: SDAH = 3,1 - 3,3 V
Is this behaviour OK? (I mean voltage 2,4V on one of the I2C high lines of the PMIC).
I2C high lines (SDAH and SCLH) are open and pulled up to 3,3 V (PMIC buck 4) on our board.
I also controlled the voltages on the low side of the translator. => OK (high level = 1,8V)
So they are wondering about the 2.4V on the high side. How is it possible that it is not 3.3V?
Regards,
Bernhard.
Hi
SDAH should be pull up to 3.3V not 2.4V,do you mind to share with us the schematic?
If a pull-up to 2.4V would be the case, then in case of SCLL(high) and SDAL(hight) the SDAH should be 2.4V. But it is 3.3V. And the customer wrote (see top of the thread): "and the SCL/SDA H side pull up to 3.3V"
I will ask the customer whether he can exclude that on his PCB the SCLH side is somehow connected to SDAH side. This would at least be an explanation for this effect.
Regards, Bernhard.
Customer detected the following:
The SWIN pin of PMIC PCA9450A is floating on our board. If I connect it to 3V3 (PMIC Buck 4), then the I2C level shifter voltage on the high side seems to be OK.
In the data sheet in Table 3 I can read for the SWIN pin: "Leave it floating if not used."
It should be made clearer in this table that in case the level shifter is used, this pin also needs to be connected.
So the issue at the customer is solved.
Regards,
Bernhard
HI
I don't fully understand your wrote.
----
SDAL and SCLL are high (1,8V) => SDAL and SCLL are high = 3,1V => OK
SDAL is high (1,8V) SCLL is low (0 V) => SDAH = 2,4 V
and
SCLH is low = 0V => I expected: SDAH = 3,1 - 3,3 V
---
When SCL/SDA low side pull up to 1.8V,and the SCL/SDA H side pull up to 3.3V ,this transistor works well,right?
what's your problem?
I draw a diagram to visualize it:
Can you test these two cases on an evaluation board?
I have no board here which would allow me to test it.
Do these level shifters have any software settings which could cause such a relation between SCL and SDA levels?
Regards,
Bernhard.
Hi Bernhard,
please have a look at the below wafeform. If there are some loads after SDAH, that can drop the voltage to 2.4V.
Can you please ask the customer to check that?
Greetings
Cornelius