Hello Harry,
It is my pleasure to help.
You are correct, the Debug mode can be confirmed by reading the fail-safe register, FS_STATES(0x18h). If bit DBG_MODE is set to 1, then the Debug mode entry is successful. Could you please confirm that all the regulators are OFF as long as VDDOTP is held high?
Once in debug mode, the next step is to verify that the device is in test mode.
After debug entry, a set of test mode keys must be sent through I2C to enter test mode.
The same set of test mode keys must be written to both the main and fail-safe test mode entry registers - M_TM_ENTRY (0x1Fh) and FS_TM_ENTRY (0x26h). Each of the keys below must be written in succession to each register
– key1: 11010101_10100111
– key2: 10111000_11101110
– key3: 00001111_00110111
After the procedure above, could you please read bit 6 of M_TM_STATUS1 (0x25h) and bit 15 of FS_STATES(0x18h) registers to verify the test mode status?
I know this process is confusing, for further information please review the chapter chapter 5.1 from the application note AN13182.
As a brief, to modify the OTP or to read the existing OTP settings the device must be in debug and test mode.
Regards,
David