GD3162 INTB ramping down

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GD3162 INTB ramping down

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Akshat_VE02376
Contributor II

Hi NXP,
GD INTB is supposed to sharply transit from 5V to 0V in the event of a fault right? But in out project we are observing a 33us delay which INTB takes to go from 5V to 0V. I have attached the snapshot. (yellow line is INTB). Can it be due to some internal logic of gate driver? Can in any scenario, features like SSD, 2LTO and SEGDRV affect INTB? Or is it due to micro itself

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JozefKozon
NXP TechSupport
NXP TechSupport

Hi Akshat, 

thank you for the schematic. I see you have connected the pull-up to the SBC_VLDO1. Please test to remove the R42 and see if the INTB fall time will decrease. Or please connect the pull-up to VDD. The recommended connection is to connect the 10k pull-up to GD3162 VDD. 

The INTB fall time is not specified, but please refer to Figure 15. in the AN13129. The typical INTB fall time in there can be seen is 10's of nanoseconds. Please download the AN13129 from the GD3162 product page, under the Secure section.

Screenshot_4.png

The INTB and FSENB connecting in HW is not safe. The INTB and FSENB pins shouldn't be connected together. This can be also reason for the long INTB fall time. The INTB should be connected only to your MCU. For the recommended FSENB pin connection please refer to the section 7.4 "Fault management in Fail-safe mode" in the AN13129.

With Best Regards,

Jozef

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JozefKozon
NXP TechSupport
NXP TechSupport

Hi Akshat, 

yes, the INTB fall time should be much shorter. Please share the INTB part of the GD3162 and MCU schematic. Have you connected the INTB pin directly to MCU? Please check if there isn't an internal pull-up turned on, on the pin to which the INTB pin is connected to the MCU side. There is a 50k internal pull-up on the INTB pin in the GD3162. It is recommended to add 10kOhm or higher external pull-up resistor to VDD, close to the INTB pin. 

With Best Regards,

Jozef

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Akshat_VE02376
Contributor II

Hi,
Please specify the time delay for INTB step down which can be considered ideal to go with. Since, currently it is around 33us. I've attached the schematic for GD INTB connection on GD side as well as micro side.

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Akshat_VE02376
Contributor II

Also, clarify whether connecting INTB to FSENB in HW is safe? Since in the current HW, FSENB is shorted with INTB so that in the event of a fault, GD enters Fail safe mode and PWM is disabled.

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JozefKozon
NXP TechSupport
NXP TechSupport

Hi Akshat, 

thank you for the schematic. I see you have connected the pull-up to the SBC_VLDO1. Please test to remove the R42 and see if the INTB fall time will decrease. Or please connect the pull-up to VDD. The recommended connection is to connect the 10k pull-up to GD3162 VDD. 

The INTB fall time is not specified, but please refer to Figure 15. in the AN13129. The typical INTB fall time in there can be seen is 10's of nanoseconds. Please download the AN13129 from the GD3162 product page, under the Secure section.

Screenshot_4.png

The INTB and FSENB connecting in HW is not safe. The INTB and FSENB pins shouldn't be connected together. This can be also reason for the long INTB fall time. The INTB should be connected only to your MCU. For the recommended FSENB pin connection please refer to the section 7.4 "Fault management in Fail-safe mode" in the AN13129.

With Best Regards,

Jozef

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