FS8530: Watchdog Disable via OTP_CFG_ASIL not effective

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FS8530: Watchdog Disable via OTP_CFG_ASIL not effective

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BL_
Contributor III

Hi NXP experts,

We're using the FS8530 in our system and want to disable its watchdog for performing hardware testing.

We have followed the solution stated in the below post but it does not work.

The suggested solution is to change the value of the OTP_CFG_ASIL from SET_REG:FS85:FS_OTP:FS_MIRRORDATA:0x0040 to SET_REG:FS85:FS_OTP:FS_MIRRORDATA:0x00C0

https://community.nxp.com/t5/Power-Management/KITFS85FRDMEVM-FS8530-Turns-Itself-Off-After-5-Seconds...

After changing this value in the generated config file from excel and burning these values to OTP register using the KITFS85SKTEVM, we observed that: whenever the USB connection is removed, the FS8530 PMIC stops running after about 4s.

 

So my question is: how to correctly disable the watchdog via OTP registers ?

Thanks

BL

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CindyWen
NXP Employee
NXP Employee

Hello BL

When DBG pin is 5V, all the regulators are off. After that if DBG pin switch to 0V, FS85 power up in debug mode and all the enable regulators are on.

 

The Automatic debug mode entry circuit in AN12333 can generate 5V pulse to let FS85 power up in debug mode. In this mode , FS85 will not reset processor even if no WD refresh. FS0B can not be released under this mode.

Processor  need to send command to let FS85 exit debug mode and enter normal mode ,  then FS0B can be released in normal mode . 

 

BRs

Cindy

 

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BL_
Contributor III

Hi Tomas,

thanks for the reply.

The problem is that: in our design MPU is supplied via the FS8530 PMIC, and the MPU may takes a long time to boot and does something stuffs. So it will not be able to send commands to the PMIC before the watchdog being triggered.

Therefore the only solution for us right now is to disable the watchdog via OTP so that we don't have to worry about the PMIC and can then re-enable the watchdog in a later stage.

Additionally for the hardware debug, also as far as I understand, in DebugPin = 5V, all the regulators are Off and the MPU will not be supplied, so we cannot do the testing.

Is there a way to force the watchdog to be disabled at start-up (via OTP configuration) ?

 

Thanks,

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CindyWen
NXP Employee
NXP Employee

Hello Blen

For FS85/FS84 products, we do not allow customer to disable the WD by OTP due to functional safety reason. And if the WD is disabled in OTP , it can not be enabled after power up.  You can choose VR5500 QM parts which is pin to pin compatible with FS85/FS84.

 

Please refer to  4.3 Automatic debug mode entry  in FS85 AN12333. This circuit can generate a 5V pulse allowing FS85 power up in debug mode. WD refresh is not needed in this mode. MPU can control the DBG_EXIT bit in  FS_STATES register to exit the debug mode and enter normal mode. MCU can do the initialization , WD refresh and FS0B release operation after that.

 

Brs

Cindy.

 

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BL_
Contributor III

Hello Cindy,

Thanks for the information. Unfortunately the option to go to Debug mode is not a solution for us.

The 1st problem is:

  • If I understand correctly, in Debug mode all the regulators are OFF. And since the MPU and its peripheries are supplied by FS85 regulators, so if the regulators are OFF then the MPU will not run and cannot be used to control the FS85 PMIC.

 

2nd problem is:

  • Additionally, in our design the PGOOD signal is also used to hold the MPU in reset, so that all peripheries are properly supplied before the MPU starts. And since the MPU takes quite some time for booting process, it will not be able to reset the PMIC via I2C in time.

 

So my questions are:

  • Do I understand the Debug Mode behavior correctly ? Or Is it that the MPU and its peripheries can be also supplied even if the PMIC is in Debug mode?
  • Is there some way to overcome the watchdog refresh problem ? Otherwise the MPU will not run and  consequently the whole system will not run.

 

Thanks very much

BL

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CindyWen
NXP Employee
NXP Employee

Hello BL

When DBG pin is 5V, all the regulators are off. After that if DBG pin switch to 0V, FS85 power up in debug mode and all the enable regulators are on.

 

The Automatic debug mode entry circuit in AN12333 can generate 5V pulse to let FS85 power up in debug mode. In this mode , FS85 will not reset processor even if no WD refresh. FS0B can not be released under this mode.

Processor  need to send command to let FS85 exit debug mode and enter normal mode ,  then FS0B can be released in normal mode . 

 

BRs

Cindy

 

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BL_
Contributor III

Hi Cindy,

The Automatic debug mode entry circuit in AN12333 can generate 5V pulse to let FS85 power up in debug mode. In this mode , FS85 will not reset processor even if no WD refresh. FS0B can not be released under this mode.

Does it mean that if the entry circuit in AN12333 is used for the FS85, then the regulators (BUCK1,2,3 + LDO1,2) of the FS85 are ON and the Watchdog is OFF when VSUP is given?

 

Thanks,

BL

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CindyWen
NXP Employee
NXP Employee

Hello BL

 

Yes. Correct.

 

Brs

CIndy.

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hi Bien,

To just perform hardware testing, I would recommend using the Debug mode where the WD window is fully opened and no WD refresh is required.

Alternatively, if not using the Debug mode, it is possible to disable WD by writing 0b0000 to the WDW_PERIOD [3:0] bits during the INIT_FS phase.

Best regards,

Tomas

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