The power management chip I use is MFS2633AMDA0AD. On the hardware, I connect the debug pin to the VBOS, so once powered on, FS26 will enter debug mode.
I used the official CDD code, following the Figure 71：“”Debug mode flow chart till safety outputs release“”
The following is my operation process and phenomenon:
1. The first step is to initialize the INIT_FS register. In this step, I turn off all effects on RSTB; As shown in the flowchart: I changed the watchdog window time to IFINITE
2. Then I perform the Watchdog Refresh. From FS_DIAG_SAFETY1, the watchdog Refresh is good
3. Then I read the FLT_ERR_CNT and conduct the Watchdog Refresh to ensure that FLT_ERR_CNT is 0
4. Then the crucial part comes when I exit debug mode: DEB_EXIT==1,My MCU was reset. I also tried to skip this step and release FS0B and FS1B directly. The result was that the FS_STATES were "safe Outputs not released"
It seems that all what you are doing is correct.
Note that in Debug mode, FS0B is kept low and cannot be released.
Regarding the RSTB, please see below from the AN13850 - NXP FS26 Implementation and Behaviors.
Thanks for you reply！
I focused on FCCU and turned off FCCU monitoring (FS_I_SAFE_INPUTS.FCCU_CFG). Problem solved, but I'm not sure why ，because I turned off FCCU related reaction earlier, so it won't affect RSTB and FS0B。