I'm trying to set timing parameters for a Nor Flash working on the GPCM mode on a P2020 board.The LALE timing can be set by OR[EAD] and LCRR[EADC] per P2020RM:
EAD: External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).
0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)
1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by LCRR[EADC]).
But I did not find any rule or guide on how to set the timing for LALE. Can you give me some suggestion?
Thanks in advance.
> I did not find the the minimal required LALE pulse duration and the minimal required hold time
> in the Micron's Nor Flash datasheet.
Please request clarification from the Micron technical support.