I start to bring up card with P1022.
DDR chips are discrete., and I have one bank of ddr3 with 32 bits width. (two chips with X16 width)
The initialize process failed.
I see the ddr clock is not running.
I have one memory bank with two pairs of clock for two chips. one clock pair for every chip. is it a problem??
both clock pairs didn't run.
I check all the setup option and read the status of the configuration of the DDR.
I couldn't find problems.
MCK should appear as soon as at least one DDR_CSn_CONFIG[CS_n_EN] is set.
> I have one memory bank with two pairs of clock for two chips. one clock pair for every chip.
> is it a problem??
Write leveling normal operation is not guaranteed in this case because of violation of the following requirement:
AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM, Table 1. DDR3 designer checklist, 46:
"Ensure one clock pair is used for each chip-select. The clock pair should follow the address/command/control signal groups in fly-by topology."
I make the timing constraints for every chip so it's should meet the timing requirement.
current problem is that after the dram setup, which include set the cs to bank number #1, the two pairs of mck didn't run.