We are using P1021 in our project and working on TDM driver, we noticed that clock edge selection is not working as mentioned in QE the document.
We are using common clock and sync signal for both TX and RX sections.
It is working for CE=0, FE=1 (sample sync on rising edge and send data on rising edge), or CE=1, FE=0 (Sample sync on falling edge and send data on falling edge).
But not for other two combinations as mentioned in the QE datasheet. I mean to say that, P1021 is sending Tx data and sampling the SYNC signal on the same clock edge.
We found this by probing clock, sync and Tx data lines. Due to this we are not able to set in other modes like sample sync on rising edge and send data falling edge vice versa.
Could you please explain the reason for this?