p4080ds rcw,srio,sgmii,rgmii work together

[gaolixing]

hello,we need use SRIO,SGMII,RGMII working at the same time,i modify the RCW,at SerDes Lane Multiplexing/Configuration segment,i choose 0x16:

0x16
sRIO2 (3.125G) bank1 a-d
sRIO1 (3.125G) bank1 e-h
Debug (3.125G) bank1 i-j
4x SGMII FM2 dTSEC[1:4] bank2 a-d
4x SGMII FM1 dTSEC[1:4] bank3 a-d

i power down all lanes in serdes blank3,and i use fm1-dtsec1 for EC2 config,but the uboot can't ping the host pc after i progrma the new rcw file,thank you very much for help

[gaolixing]

ping log:

=> ping 192.168.1.126
Using FM1@DTSEC2 device
host 192.168.1.126 is alive

printenv log:

printenv
baudrate=115200
bdev=sda1
bootcmd=setenv bootargs root=/dev/mtdblock8 rootfstype=jffs2 rw console=$consoledev,$baudrate $othbootargs;bootm e8020000 - e8800000
bootdelay=3
bootfile=uImage
consoledev=ttyS0
eth1addr=00:04:9f:00:67:01
eth2addr=00:04:9f:00:67:02
eth3addr=00:04:9f:00:67:03
eth4addr=00:04:9f:00:67:04
eth5addr=00:04:9f:00:67:05
eth6addr=00:04:9f:00:67:06
eth7addr=00:04:9f:00:67:07
eth8addr=00:04:9f:00:67:08
eth9addr=00:04:9f:00:67:09
ethact=FM1@DTSEC2
ethaddr=00:04:9f:00:67:00
ethprime=FM1@DTSEC2
fdtaddr=2000000
fdtfile=uImage-p4080ds.dtb
fman_ucode=eff00000
gatewayip=192.168.1.1
hvboot=setenv bootargs console=ttyS0,115200 config-addr=0xfe8900000;bootm 0xfe8700000 - 0xfe8800000
hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;fsl_fm1_xaui_phy:xfi;fsl_fm2_xaui_phy:xfi
ipaddr=192.168.1.50
loadaddr=1000000
netdev=eth0
netmask=255.255.255.0
nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr
ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr
ramdiskaddr=5000000
ramdiskfile=fsl-image-mfgtool-p4080ds.ext2.gz.u-boot
rootpath=/opt/nfsroot
sataboot=setenv bootargs root=/dev/sda1 rootdelay=5 rw console=$consoledev,$baudrate $othbootargs;bootm e8020000 - e8800000
serverip=192.168.1.126
stderr=serial
stdin=serial
stdout=serial
tftpflash=tftpboot $loadaddr $uboot && protect off $ubootaddr +$filesize && erase $ubootaddr +$filesize && cp.b $loadaddr $ubootaddr $filesize && protect on $ubootaddr +$filesize && cmp.b $loadaddr $ubootaddr $filesize
uboot=u-boot-nor.bin
ubootaddr=0xeff80000

Environment size: 1862/8188 bytes

[gaolixing]

hello,the follow is 0x13 config log:

uboot log:

U-Boot 2019.04+fsl+gc873063750 (May 21 2020 - 06:18:18 +0000)

CPU0: P4080E, Version: 3.0, (0x82080030)
Core: e500mc, Version: 3.1, (0x80230031)
Clock Configuration:
CPU0:1499.985 MHz, CPU1:1499.985 MHz, CPU2:1499.985 MHz, CPU3:1499.985 MHz,
CPU4:1499.985 MHz, CPU5:1499.985 MHz, CPU6:1499.985 MHz, CPU7:1499.985 MHz,
CCB:799.992 MHz,
DDR:649.994 MHz (1299.987 MT/s data rate) (Asynchronous), LBC:399.996 MHz
FMAN1: 599.994 MHz
FMAN2: 599.994 MHz
QMAN: 399.996 MHz
PME: 599.994 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 105a0000 00000000 1e1e181e 0000cccc
00000010: 4c400400 003c2000 de800000 e1000000
00000020: 00000000 00000000 00000000 008be000
00000030: 00000000 00000000 00000000 00000000
Board: P4080DS, Sys ID: 0x17, Sys Ver: 0x01, FPGA Ver: 0x0c, vBank: 0
SERDES Reference Clocks: Bank1=100MHz Bank2=125MHz Bank3=125MHz
I2C: ready
DRAM: Initializing....using SPD
Detected UDIMM i-DIMM
Detected UDIMM i-DIMM
Not enough bank(chip-select) for CS0+CS1 on controller 0, interleaving disabled!
Not enough bank(chip-select) for CS0+CS1 on controller 1, interleaving disabled!
2 GiB left unmapped
Testing 0x00000000 - 0x7fffffff
Testing 0x80000000 - 0xffffffff
Remap DDR 2 GiB left unmapped

2 GiB (DDR3, 64-bit, CL=9, ECC on)
DDR Controller Interleaving Mode: cache line
POST memory PASSED
Flash: 128 MiB
L2: 128 KiB enabled
Corenet Platform Cache: 2 MiB enabled
Warning: SERDES8 requires banks two and three to be disabled in the RCW
SRIO1: enabled but port error
SRIO2: enabled but port error
MMC: FSL_SDHC: 0
Loading Environment from Flash... OK
EEPROM: CRC mismatch (998e1e41 != ffffffff)
PCIe1: disabled
PCIe2: disabled
PCIe3: disabled
In: serial
Out: serial
Err: serial
Warning: SERDES bank 2 expects reference clock 100MHz, but actual is 125MHz
Net: Fman1: Uploading microcode version 106.2.18
Could not get PHY for P4080DS_MDIO3: addr 4
Failed to connect
Fman2: Uploading microcode version 106.2.18
Could not get PHY for P4080DS_MDIO1: addr 0
Failed to connect
FM1@DTSEC2 [PRIME], FM1@TGEC1, FM2@TGEC1
Hit any key to stop autoboot: 0

[ufedor]

It was requested to ATTACH logs and not insert them inline - please do it next time.

Please provide (as textual attachments) CCSR registers dumps (by U-Boot md.l command) for the FM1@DTSEC2 corresponding to SerDes protocols 0x13 and 0x16.

Please correct all warnings like the following:

Warning: SERDES bank 2 expects reference clock 100MHz, but actual is 125MHz

[gaolixing]

ping log:

ping 192.168.1.126
Using FM1@DTSEC2 device

ARP Retry count exceeded; starting again
ping failed; host 192.168.1.126 is not alive

when i use 0x13 for for SRDS_PRTCL setting,the RGMII is ok

[ufedor]

> when i use 0x13 for for SRDS_PRTCL setting,the RGMII is ok

Please attach log corresponding to this case.

[gaolixing]

thanks,follow is the logs

uboot log:

U-Boot 2019.04+fsl+gc873063750 (May 21 2020 - 06:18:18 +0000)

CPU0: P4080E, Version: 3.0, (0x82080030)
Core: e500mc, Version: 3.1, (0x80230031)
Clock Configuration:
CPU0:1499.985 MHz, CPU1:1499.985 MHz, CPU2:1499.985 MHz, CPU3:1499.985 MHz,
CPU4:1499.985 MHz, CPU5:1499.985 MHz, CPU6:1499.985 MHz, CPU7:1499.985 MHz,
CCB:799.992 MHz,
DDR:649.994 MHz (1299.987 MT/s data rate) (Asynchronous), LBC:399.996 MHz
FMAN1: 599.994 MHz
FMAN2: 599.994 MHz
QMAN: 399.996 MHz
PME: 599.994 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 105a0000 00000000 1e1e181e 0000cccc
00000010: 58400400 003c2000 de800000 e1000000
00000020: 00000000 00000000 00000000 008be000
00000030: 00000000 00000000 00000000 00000000
Board: P4080DS, Sys ID: 0x17, Sys Ver: 0x01, FPGA Ver: 0x0c, vBank: 0
SERDES Reference Clocks: Bank1=100MHz Bank2=125MHz Bank3=125MHz
I2C: ready
DRAM: Initializing....using SPD
Detected UDIMM i-DIMM
Detected UDIMM i-DIMM
Not enough bank(chip-select) for CS0+CS1 on controller 0, interleaving disabled!
Not enough bank(chip-select) for CS0+CS1 on controller 1, interleaving disabled!
2 GiB left unmapped
Testing 0x00000000 - 0x7fffffff
Testing 0x80000000 - 0xffffffff
Remap DDR 2 GiB left unmapped

2 GiB (DDR3, 64-bit, CL=9, ECC on)
DDR Controller Interleaving Mode: cache line
POST memory PASSED
Flash: 128 MiB
L2: 128 KiB enabled
Corenet Platform Cache: 2 MiB enabled
Warning: SERDES8 requires banks two and three to be disabled in the RCW
SERDES: timeout resetting bank 3
SRIO1: enabled but port error
SRIO2: enabled but port error
MMC: FSL_SDHC: 0
Loading Environment from Flash... OK
EEPROM: CRC mismatch (998e1e41 != ffffffff)
PCIe1: disabled
PCIe2: disabled
PCIe3: disabled
In: serial
Out: serial
Err: serial
Warning: SERDES bank 1 expects reference clock 125MHz, but actual is 100MHz
Warning: SERDES bank 3 expects reference clock 100MHz, but actual is 125MHz
Net: Fman1: Uploading microcode version 106.2.18
Could not get PHY for P4080DS_MDIO12: addr 28
Failed to connect
Could not get PHY for P4080DS_MDIO12: addr 30
Failed to connect
Could not get PHY for P4080DS_MDIO12: addr 31
Failed to connect
Fman2: Uploading microcode version 106.2.18
Could not get PHY for P4080DS_MDIO4: addr 28
Failed to connect
Could not get PHY for P4080DS_MDIO4: addr 29
Failed to connect
Could not get PHY for P4080DS_MDIO4: addr 30
Failed to connect
Could not get PHY for P4080DS_MDIO4: addr 31
Failed to connect
FM1@DTSEC1, FM1@DTSEC2 [PRIME], FM1@DTSEC3, FM1@DTSEC4, FM2@DTSEC1, FM2@DTSEC2, FM2@DTSEC3, FM2@DTSEC4
Hit any key to stop autoboot: 0

###################################################################################

printenv log:

printenv
baudrate=115200
bdev=sda1
bootcmd=setenv bootargs root=/dev/mtdblock8 rootfstype=jffs2 rw console=$consoledev,$baudrate $othbootargs;bootm e8020000 - e8800000
bootdelay=3
bootfile=uImage
consoledev=ttyS0
eth1addr=00:04:9f:00:67:01
eth2addr=00:04:9f:00:67:02
eth3addr=00:04:9f:00:67:03
eth4addr=00:04:9f:00:67:04
eth5addr=00:04:9f:00:67:05
eth6addr=00:04:9f:00:67:06
eth7addr=00:04:9f:00:67:07
eth8addr=00:04:9f:00:67:08
eth9addr=00:04:9f:00:67:09
ethact=FM1@DTSEC2
ethaddr=00:04:9f:00:67:00
ethprime=FM1@DTSEC2
fdtaddr=2000000
fdtfile=uImage-p4080ds.dtb
fman_ucode=eff00000
gatewayip=192.168.1.1
hvboot=setenv bootargs console=ttyS0,115200 config-addr=0xfe8900000;bootm 0xfe8700000 - 0xfe8800000
hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;fsl_fm1_xaui_phy:xfi;fsl_fm2_xaui_phy:xfi
ipaddr=192.168.1.50
loadaddr=1000000
netdev=eth0
netmask=255.255.255.0
nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr
ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr
ramdiskaddr=5000000
ramdiskfile=fsl-image-mfgtool-p4080ds.ext2.gz.u-boot
rootpath=/opt/nfsroot
sataboot=setenv bootargs root=/dev/sda1 rootdelay=5 rw console=$consoledev,$baudrate $othbootargs;bootm e8020000 - e8800000
serverip=192.168.1.126
stderr=serial
stdin=serial
stdout=serial
tftpflash=tftpboot $loadaddr $uboot && protect off $ubootaddr +$filesize && erase $ubootaddr +$filesize && cp.b $loadaddr $ubootaddr $filesize && protect on $ubootaddr +$filesize && cmp.b $loadaddr $ubootaddr $filesize
uboot=u-boot-nor.bin
ubootaddr=0xeff80000

Environment size: 1862/8188 bytes

[gaolixing]

thanks,you are right,we use EC2 with FM1-dTSEC2,now we use 0x16 for SRDS_PRTCL setting

[gaolixing]

thanks,you are right,we use EC2 with FM1-dTSEC2,now we use 0x16 for SRDS_PRTCL setting,we need two SRIO in serdes blank1,one SGMII for serdes blank2,serdes blank3 is not used,we also need FM1-dTSEC2 as RGMII at EC2,i have power down serdes blank3,but RGMII still not work,how can i fix it? thank you

[ufedor]

Please provide as textual attachment a log containing:

1) U-Boot booting

2) environment variables (printenv)

3) ping attempt

[ufedor]

> fm1-dtsec1 for EC2 config

There is no such option - either FM2-dTSEC1 or FM1-dTSEC2.

Also please ensure that the following note from the P4080 QorIQ Multicore Communication Processor Reference Manual, Table 4-35. RCW Field Descriptions is fulfilled:

"If SGMII mode is to be used (with the appropriate SerDes lane powered on in SRDS_LPDn) for FM2-dTSEC1 or FM1- dTSEC2, then RGMII mode for that dTSEC must not be enabled in EC2. However, if RGMII is to be used by FM2-dTSEC1 or FM1-dTSEC2 and EC2 is set accordingly, then SGMII mode must not be enabled for FM2-dTSEC1 or FM1-dTSEC2 (and the corresponding SerDes lane must be powered down in SRDS_LPD_Bn if SGMII is selected for that bank n in the SRDS_PRTCL setting)."