p3041 reset platform clock frequency


p3041 reset platform clock frequency

559 次查看
Contributor I

We are trying to get the CPU to read the RCW during boot. On the P3041, If the SYSCLK input is 83.3 Mhz, what will be the Platform Clock frequency and the subsequent ELBC clock frequency when the processor reads the RCW from NOR flash. Since the PLLs are not up at that time. The P3041RM is vague on how the platform clock and/or the ELBC clock behave during reset while reading the RCW from NOR. We are seeing an approximate 5Mhz ELBC clock while reading the RCW.

secondly, is there any errata regarding booting from 32 bit flash? When we boot with the codewarrior tap, we can read and write the flash properly so it seems to be interfaced correctly. We have programmed the RCW in flash and it is correct by inspection with codwarrior.

标签 (1)
标记 (2)
0 项奖励
1 回复

281 次查看
NXP Employee
NXP Employee

As far as I can understand, reset controller is completely independent block, it does not bring up platform PLL before loading RCW data.

Reference manual says:

Initially, the RCW source POR configuration inputs are sampled to determine the

configuration source. Next, the device begins loading the RCW data. The system PLL

begins to lock according to the clock ratio/mode values communicated in the RCW data.

For second question - I do not see any errata related to booting from 32-bit eLBC GPCM NOR flash, nor to PBI loading.

0 项奖励