p2040 sgmii mode rcw settings

[dickginther]

I am confused about the setting for SRDS_RATIO_B1, SRDS_DIV_B1, SRDS_RATIO_B2 and SRDS_RATIO_B2 in the P2040 RCW.  I am using all five SGMII interfaces and have the SRDS_PRTCL set to 0x14.  I have 125MHz on both SD_REF_CLK1 and SD_REF_CLK2 inputs.  In the notes for SRDS_DIV_1/2 it

states "lanes configured as SGMII operate at 1.25Gbps regardless of the corresponding SRDS_DIV_B1 settings."

For SGMII interfaces are the SRDS_RATIO_B1/B2 settings also invalid?  Does the chip just use the 125MHz input and automatically use a 10:1 ratio for SGMII?

[lunminliang]

I think you can refer to Section 4.6.5.3 Reference Clocks for SerDes Protocols, Table 4-36 Valid SerDes RCW Encodings and Referenc Clocks in P2040RM.pdf.

The state means if you use SGMII 1.25Gbps, the valid SD_REF_CLK should be 100MHz or 125MHz, and the corresponding valid SRDS_RATIO_B should be 50:1 and 40:1, for your case it should be 40:1, in such operation, SerDes bank is configured for 5 Gbps, lanes configured as SGMII operate at 1.25Gbps, do not care the value of SRDS_DIV_B.