p1012: hdlc: when hdlc tx/rx feed with different frequency external clock, rx can not receive data

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

p1012: hdlc: when hdlc tx/rx feed with different frequency external clock, rx can not receive data

837 Views
carlpeng
Contributor II

Hello,

I encounter a very strange issue about HDLC.

For the HDLC,  in my design, uses external clock, 

during debug,  find that, if feed the HDLC's rx/rx clock with different frequency clock, HDLC rx channel

will can not receive data any more.

Does it need to do some special setting for HDLC if RX/TX clock is different frequency?

Could you help to give some suggestions?

Labels (1)
0 Kudos
4 Replies

569 Views
alexander_yakov
NXP Employee
NXP Employee

Could you please draw the exact connection circuit of both sides P1012 and remote device, and both TX and RX side, and show how exactly (from which source) the clock is applied for all four cases (P1012tx, P1012rx, remote tx, remote tx).


Have a great day,
Alexander

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos

569 Views
carlpeng
Contributor II

Hello Alexander,

Thanks a lot!

I use the different HDLC peripherals of the same P1021 chip to communicate. The connection relationship is as below:

pastedImage_2.png 

As the above figure said:

txclk_hdlc0, rxclk_hdlc1: 8M

rxclk_hddlc0, txclk_hdlc1: 16M

we have done the below experiments:

1) use 16M clock to communicate

    That is, HDLC1 send and HDLC0 receive, there are only send interrupt and no receive interrupt, receive side 

     can not receive data;

2) use 8M clock to communicate

    That is, HDLC0 send and HDLC1 receive, there are send interrupt and receive interrupt, but the receive side

    will pop out error in the BD status field.

Thank you!

Carl

0 Kudos

569 Views
alexander_yakov
NXP Employee
NXP Employee

Sorre, the figure is not clear, please answer following questions.

1. Please confirm txclk_hdlc0 and rxclk_hdlc1 is the same clock, sourced from the same (one) clock source.

2. Please confirm rxclk_hddlc0 and txclk_hdlc1 is the same clock, sourced from the same (one) clock source.

0 Kudos

569 Views
carlpeng
Contributor II

Hello Alexander,

yes,

1. Please confirm txclk_hdlc0 and rxclk_hdlc1 is the same clock, sourced from the same (one) clock source.

yes, txclk_hdlc0 and rxclk_hdlc1 is from the same crystal oscillator with 8M frequency.

2. Please confirm rxclk_hddlc0 and txclk_hdlc1 is the same clock, sourced from the same (one) clock source.

yes, rxclk_hddlc0 and txclk_hdlc1 is from the same crystal oscillator with 16M frequency.

Thanks a lot

Carl

0 Kudos