We are using P1010 e500V2 processor I have following doubt:
I want to understand , if we open three TLB which has overlapped address , what all bad things can happen in a system, TLBs entry is shown below:
TLB_1_0 = Base Address 0xF0000000 , SIZE = 256 MB , Target Device = Parallel Flash(boot flash) , Attributes = cache inhibited , write through , executable , Guarded (though we have open the 256 MB window the base address of the boot flash is 0xFc000000)
TLB_1_1 = Base Address 0xF0000000, SIZE = 64 MB, Target Device = FPGA 1, Attributes = cache inhibited , write through , Guarded
TLB_1_2 = Base Address 0xF0200000, SIZE = 128 KB, Target Device = FPGA 2, Attributes = cache inhibited , write through , Guarded
In above TLB'S virtual Address = Physical Address.
My purpose of asking this question is that we are seeing very weird behavior in the system, some time when we try to write to 0xF0200000 where we have mapped FPGA 2 that write goes to FPGA 1 which is mapped to 0xF0000000.
Can the above overlapping of TLBS can cause this problem..?
Please refer to the PowerPC e500 Core Family Reference Manual, 12.2.3 Checking for TLB Entry Hit:
“A hit to multiple matching TLB entries is considered a programming error. If this occurs, the TLB generates an invalid address and TLB entries may be corrupted (an exception is not reported).”
Thanks for the reply. So if we have multiple TLB for same address , then you are saying we can face the problem when we are trying to write to one of the FPGA which is mapped at address 0xF0000000 that write can go to other FPGA which is mapped at 0xf0200000, due to same addresses present in multiple TLBs. If Yes, can you please elaborate the same with an example.
Thanks for the TCL script. But I am not looking for how to solve the overlap problem. That I can solve. But what I don't understand is how a overlap TLB's can cause a write to some address go to other address. What we see in our experiment is when we are writing a value 0f 0x6666 to address 0xf0200000 this write goes to 0xf0000000, and this we are not able to understand how it can happen. Is overlap TLB's can cause this issue is my question and if yes how..?