how to set watchdog on P1020 custom board

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how to set watchdog on P1020 custom board

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francescoluccon
Contributor I

I'm lately working on a custom board with P1020 cpu, and I have to setup watchdog timer in u-boot but following the patches achived by denx and by mpc85xx supporters for a similar board (see link [U-Boot] CPU Wachtog for P2041) I still haven't solved the issue. I've noticed that after the initialization of watchdog done by  init_85xx_watchdog() function during my debug, the HRESET_B_REQ output signal is still high. Can you help me?

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jeypatel
Contributor I

Hi,

I want to enable watchdog in uboot 2011-12 provided by freescale for p1020rdb boards.

When I enable CONFIG_WATCHDOG I observed some undefined reference errors, however I solved.

But I am unable to trigger the watchdog from uboot ( RTC ds1339 chip)

- I applied "http://osdn.jp/users/mark_n2/pf/uboot/scm/commits/dcdb61a084bd3840d0987a5d01ae506c11efca1b" commit patch. Still no progress.

- Can someone point me out how to set and configure watchdog in watchdog.

- I found that for p2020 boards, "wdg" command is supporting for enable/disable watchdog functionality.

  But it seems p1020 boards are not supporting this command.

- Another thing I observed that when I am doing probe for valid chip address nothing is detected using the command "i2c probe".

Thanks in advance.

- francescolucconi​, can you please help me on it if you got success achieving the watchdog functionality in uboot ?

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jeypatel
Contributor I

Hi Francesco Lucconi,

Thanks for your help. I am able to implement watchdog functionality in uboot and it is working fine.

I want to check the  reset reason i.e Power On Reset or Watchdog Reset. From the reference manual I figure out that

"GUTS_MCPSUMR", "GUTS_AUTORSTSR", "GUTS_RSTRSCR" register should contain the reset reason,

however when I printed in  Uboot source code, it was '0' after reset.

How can i find out the reason of the status register not updating.

I am wondering where and how these registers are not updating after reset???

Am i missing something or need to enable anything to find-out the reset status(Watchdog Reset or Power On Reset) ?

Can you please help me out on it?

Thanks & regards,

Jey

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jeypatel
Contributor I

Hi francescolucconi

Thank you for your quick response and patches.

I already applied the 1st 4 patches and the patches kmp204x is not applying.

Still the watchdog functionality is not working in uboot.

I am enabling CONFIG_WATCHDOG  in "configs/p1_p2_rdb_pc.h " to enable watchdog.

I observed undefined reference error while compiling uboot source code for NAND.

uboot-custom/nand_spl/board/freescale/p1_p2_rdb_pc/cache.c:39: undefined reference to `watchdog_reset'

uboot-custom/nand_spl/board/freescale/p1_p2_rdb_pc/cache.c:47: undefined reference to `watchdog_reset'

ns16550.o: In function `NS16550_putc':

uboot-custom/nand_spl/board/freescale/p1_p2_rdb_pc/ns16550.c:97: undefined reference to `watchdog_reset'

However I modified the code to build without errors.

Did you port the patches 4 to 9(kmp204x) for p1020rdb board?

Should I need to set or modified something else to make watchdog work in uboot?

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yipingwang
NXP TechSupport
NXP TechSupport

Hello Francesco,

Can you execute "reset" command in u-boot?

Would you please provide some example codes to show how you used Watchdog timer in u-boot?

Do you use Freescale Linux SDK?


Have a great day,
Yiping

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francescoluccon
Contributor I

Hi Yiping,

I can't execute reset command, the system hangs up after its execution. As I noticed this is due to an hardware problem (HR_RESET_REQ is not connected to CPLD chip and for this reason the hardware reset is not driven by the CPLD logic).

To test watchdog timer I've applied a while(1) cycle whithin 'version' command, and using that command into the command line I waited unsuccessfully the watchdog activation.

I've done this test using u-boot-2011.12 from Freescale Linux SDK.

Regards,

Francesco

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yipingwang
NXP TechSupport
NXP TechSupport

Hello Francesco,

I don't have this version u-boot source code, I think you could add some code to print prompt information in Watchdog Exception handler to check whether the watchdog timer timeout interrupt is enabled.


Have a great day,
Yiping

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francescoluccon
Contributor I

Hi Yiping,

As you wrote, I've noticed through e500v2 CPU documentation and with u-boot/kernel source code that P1020 watchdog setup has been done with the activation of its relative interrupt and therefore there's a registration of a watchdog handler linked with the wdt interrupt. Instead I want to setup the booke watchdog avoiding the use of its corresponding interrupt because it has to be active although the system hangs up. Is there a way to deploy that?

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scottwood
NXP Employee
NXP Employee

If you don't want to take the interrupt, clear TCR_WIE -- but even if you leave the interrupt enabled, you'll still get the reset on the next watchdog expiration, as long as the interrupt doesn't clear the watchdog.

What value have you set in TCR, and how long did you wait for the watchdog?  Have you disabled interrupts, or removed WATCHDOG_RESET from timer_interrupt()?

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yipingwang
NXP TechSupport
NXP TechSupport

Hello Francesco,

Please refer to the following code and check whether HRESET_REQ is asserted.

1. define CONFIG_WATCHDOG 

2. #include/watchdog.h

3. while(1)

{

#if defined(CONFIG_HW_WATCHDOG)

        WATCHDOG_RESET ();     

#endif  /* CONFIG_HW_WATCHDOG */

}


Have a great day,
Yiping

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