can we add exception on QE0 pin in p1025?

[senoghte]

Hi all,

P1025 QE0 convolve a lot of pins as you see below.  can we add exception on some of these pins? 

for example can we set QE0 to 0 but CE_PB[10] treat as QE0 is 1?

my problem is on PB10 that alternate function is ENET5_TXD[1].

Regards

CE_ PA4	LA16	QE0	LA16	UPC1_ TxDATA[ 8]	ENET1_ RX_DV	TDMA_T XD[0]	SER1_ CTS	-	-	-	-
CE_ PA5	LA17	QE0	LA17	UPC1_ TxDATA[ 9]	ENET1_ TX_EN	TDMA_ RXD[0]	SER1_ RTS	-	-	-	-
CE_ PA6	LA18	QE0	LA18	UPC1_ TxDATA[ 10]	ENET1_ RXD[0]	TDMA_ TSYNC	SER1_ RXD[0]	-	-	-	BRGO9
CE_ PA7	LA19	QE0	LA19	UPC1_T xDATA[1 1]	ENET1_ TXD[0]	TDMA_R SYNC	SER1_ TXD[0]	-	-	-	BRGO10
CE_ PA8	LA20	QE0	LA20	UPC1_ TxDATA[ 12]	ENET1_ RX_ER	TDMA_R EQ	SER1_ CD	-	-	-	-
CE_ PA9	LA21	QE0	LA21	UPC1_ TxDATA[ 13]	ENET1_ TXD[1]	-	-	-	-	-	-
CE_ PA10	LA22	QE0	LA22	UPC1_ TxDATA[ 14]	ENET1_ RXD[1]	-	-	-	-	-	-
CE_ PA11	LDP0	QE0	LDP0	UPC1_ TxDATA[ 15]	ENET1_ TXD[2]	TDMB_R XD[1]	SER3_ RXD[1]	-	-	-	-
CE_ PA12	LDP1	QE0	LDP1	UPC1_ RxDAT A[8]	ENET1_ TXD[3]	TDMB_R XD[2]	SER3_ RXD[2]	-	-	-	-
CE_ PA13	LA28	QE0	LA28	UPC1_ RxDAT A[9]	ENET1_ TX_ER	TDMB_R XD[3]	SER3_ RXD[3]	-	-	-	-
CE_ PA14	LGPL5	QE0	LGPL5	UPC1_ RxDAT A[10]	ENET1_ RXD[2]	TDMB_T XD[1]	SER3_ TXD[1]	-	-	-	-
CE_ PA16	LCLK1	QE0	LCLK1	UPC1_ RxDAT A[12]	ENET1_ COL	TDMB_T XD[3]	SER3_ TXD[3]	-	-	-	-
CE_ PA17	LA23	QE0	LA23	UPC1_ RxDAT A[13]	ENET1_ CRS	-	-	-	-	-	-
CE_ PA18	LA24	QE0	LA24	UPC1_ RxDAT A[14]	-	TDMD_T XD[0]	SER7_ CTS	1588_clk_out	-	-	-
CE_ PA19	LA25	QE0	LA25	UPC1_ RxDAT A[15]	-	TDMD_ RXD[0]	SER7_ RTS	1588_pulse_ou t1	-	-	-
CE_ PA20	LA26	QE0	LA26	UPC1_ TxPRTY	-	TDMD_ TSYNC	SER7_ RXD[0]	1588_trig_out	-	-	BRGO9
CE_ PA21	LA27	QE0	LA27	UPC1_ RxPRTY	-	TDMD_ RSYNC	SER7_ TXD[0]	1588_tri g_in	-	-	BRGO11
CE_ PA22	LCS4_B	QE0	LCS4_B	UPC1_ RxSOC	-	TDMD_R EQ	SER7_ CD	1588_pt p_clk	-	-	-
CE_ PA23	LCS5_B	QE0	LCS5_B	UPC1_ TxSOC	-	-	-	-	-	CLK1, CLK12	BRGO1
CE_ PA24	LCS6_B	QE0	LCS6_B	UPC1_ RxCLAV[ 0]	-	-	-	-	RISC_ GPIO[4]	CLK9	BRGO2
CE_ PA25	LA29	QE0	LA29	UPC1_ TxCLAV[ 0]	-	-	-	-	RISC_ GPIO[5]	-	-
CE_ PA26	LA30	QE0	LA30	UPC1_ TxEN[0]	-	-	-	-	-	-	-
CE_ PA27	LCS7_B	QE0	LCS7_B	UPC1_ RxEN_B[ 0]	-	-	-	-	-	CLK6, CLK11	BRGO1
CE_ PA30	LA31	QE0	LA31	UPC1_ TxADD R[2]	-	TDMB_ TSYNC	SER3_ RXD[0]	-	-	-	-
CE_ PB10	IRQ6	QE0	IRQ6	-	ENET5_ TXD[1]	-	-	-	RISC_ GPIO[14	CLK7, CLK16	BRGO5

[alexander_yakov]

The only 10 QE port pins may be used to generate interrupts - PA4 PA8 PA18 PA22 PA28 PB0 PB4 PB8 PB14 PB18

Please look P1025 Reference Manual, Sections 3.5.3 and 3.5.4 for more information.

Have a great day,
Alexander

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