Why does HRESET_REQ# pin of P1011 always output low ?

[yuanqiangwang]

Hello,

    I am verifying a P1011 board which designed by myself. Now, u-boot run ok, uart, eTSEC, pcie all works. But I find that the HRESET_REQ# pin always output low after HRESET# deasserts. When HRESET# asserts, the HRESET_REQ# turns high. Only a 4.7K pull-up resistor connects this pin. Boot sequencer is disabled. Can you tell me what cause this situatuion ?

[r8070z]

Have a great day,

You may check the reset request status and control register (GUTS_RSTRSCR) in order to get reason for the HRESET_REQ# assertion. Besides of Boot sequence reset request there are Watchdog timer reset request, Software settable reset request, NAND Flash ECC error during boot reset request. These reasons may not crush systems and u-boot can run with uart, eTSEC and pcie. For example watchdog can be enabled but is not treated in time or even not treated at all. It just assigns the HRESET_REQ# and nothing more.

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[yuanqiangwang]

I check the relative registers, their value is followed. GUTS_RSTRSCR is 0x00000000, GUTS_ECTRSTCR is 0x00000000, GUTS_AUTORSTSR is 0x040080000. The value shows that Core1 was reset in response to its watchdog timer expiration. Is this the reason of HRESET_REQ# assertion ? But my CPU is P1011, there is not core1 on the chip. Is the watach dog enabled default after power on ? and, How to disable it ?

[yuanqiangwang]

I check the relative registers, their value is followed. GUTS_RSTRSCR is 0x00000000, GUTS_ECTRSTCR is 0x00000000, GUTS_AUTORSTSR is 0x040080000. The value shows that Core1 was reset in response to its watchdog timer expiration. Is this the reason of HRESET_REQ# assertion ? But my CPU is P1011, there is not core1 on the chip. Is the watach dog enabled default after power on ? and, How to disable it ?