Why SRAM of NAND FCM can't be modified on P1010?

[ktx]

Hi,

We have a P1010RDB and our own PCB design which is very similar to the P1010RDB.

The processor on P1010RDB is P1010E(rev1.0), our board is P1010(rev2.1) whick has no E(security)。

We have checked the Processor version register (PVR) and system version register (SVR) in u-boot:

P1010RDB

=> md ffee00a0

ffee00a0: 80212151 80f90010 00000010 00000000    .!!Q............

ffee00b0: 00000000 00000000 00000000 00000000    ................

Our board

=> md ffee00a0

ffee00a0: 80212152 80f10020 00000010 00000000    .!!R... ........

ffee00b0: 00000000 00000000 00000000 00000000    ................

Because u-boot cann’t detect the nand chip on our board,we tried many ways to solve the problem,finally we find maybe something is wrong with the SRAM buffer used by NAND FCM.The datasheet says:“Read and write accesses to IFC banks controlled by NAND FCM do not access attached NAND flash EEPROMs directly. Rather, these accesses read and write the buffer RAM (a single, shared 16-KB space internal to the IFC and mapped by the base address of

every NAND FCM bank).” With codewarrior and usb tap,we find we can modified the sram buffer on P1010RDB,but we cannt do this on our board because the sram is all zero.

Here is our step:

1 codewarrior version(evaluation)

- CodeWarrior for Power Architecture

          Version: 10.5.0

          Build Id:150709

2 create a new bareboard project,select board P1010RDB.

3 change nothing.

4 build the project.

5 connect the USB TAP to P1010RDB,start debug,the program stop at the main entrypoint.

6 check the memory 0xEFA00000( sram buffer) in the memory view,the data are random.We can modify addr 0x0(DDR) and 0xEFA000000(SRAM):

7 use the same project with our board,we find the memory 0xEFA00000( sram buffer) is filled all zero,and we can modify addr 0x0(DDR) , we cann’t modify 0xEFA00000(SRAM).

We also create a new project which select board P1010RDB-PB,but all is the same.

We are sure the NAND chip is not relevant,because after we modified the P1010RDB-PB_init_core.tcl and make CS2 to NAND FCM( nothing is conned to CS2 on P1010RDB and our board),all is the same.

We rechecked the datasheet and didn’t find some useful information. So,What can we do next? Maybe there is some difference between P1010 and P1010E? Maybe we missed some important step?

If you have any ideas please help us, and thanks!

[ktx · Accepted solution]

With the quick and professional help of NXP technical support，we finally find it is related to the hardware.

When we remove the 4.7Kohm pull-down resistor of UART_SOUT_0,the sram of nand fcm can be modified.

***********************************

> d) low UART_SOUT_0 (connect to MAX2232,with 4.7Kohm pull-down resistor)

Please refer to the P1010 QorIQ Integrated Processor Hardware Specifications, Table 1. P1010 pinout listing, Note 7:

“This pin must NOT be pulled down, by a resistor or the component it is connected to, during power-on reset.”

This note has to be fulfilled for the UART_SOUT_0.

***********************************

Many many thanks to ufedor and NXP support, you are so great!

[jingxixi]

Hi,all.

What I wondered is 'Is there any difference between P1010 and P1010E other than the SEC' or maybe there are some registers not open to the ordinary user that can active the NAND SRAM. Further more,Is there somebody who use P1010(not P1010E)'s NAND successfully.

I am sure the schematic is correct,also when i read nandid in the codewarrior i can see the nand can respond with 0x2c 0xdc 0x90 0x95 0x56 in chipscope,but this data do not come to SRAM,so i cannt get the right id-value but all zeros,  and come to the

"Why SRAM of NAND FCM can't be modified on P1010?"

Why? I am so confusing!

Any suggestion is appreciated!

Best Regards

Xixi

[ktx]

ufedor:

you can find the the schematics pdf (p1010 connection) in the attachment.

I have created a Service Request for this problem which is Case 00074287.

Thank you for your advice, maybe someone can help me out of the mess.

[ufedor]

Please consider creating a technical case:

How I could create a Service Request?

[ufedor]

How many boards were tested?

Could you provide the processor connection schematics as searchable PDF?

[ktx]

We have tested two boards，same trouble。

Maybe I can't post the schematics here.

Can I have your email? When I get the schematics pdf from my colleague, I can email that to you.

Thank you again。

[ktx]

ufedor​:

If I misunderstand your words, please let me know.

Thank you for your time and patience。

[ktx]

ufedor​

Maybe i didn't say clearly, here is the detail:

1  With codewarrior + usbtap,  if we modify IFC configuration in the P1010RDB-PB_init_core.tcl, we can see the the new value in the register view. We can also modify the IFC reg in the register view.

2 We dumped all the register on both boards and compared them. I am sure LAW are the same.

rdb_all.txt: P1010RDB

our_all.txt: Our board

[ufedor]

1) Please use a debugger to check that IFC registers are writable on the problem board.

2) Please confirm that you have compared LAW memory dumps on both boards.

[ktx]

ufedor:

1 IFC registers can be modified on our board, as i had said,"We are sure the NAND chip is not relevant,because after we modified the P1010RDB-PB_init_core.tcl and make CS2 to NAND FCM( nothing is conned to CS2 on P1010RDB and our board),all is the same."

There is a nor flash chip connected on CS 0, after programmed U-boot on nor, our board boot ok.

2 LAW registers are the same on both boards.

[ktx]

Thank you for your advice, ufedor.

Here is the result:

P1010RDB:                              

GUTS_DEVDISR1 0x02403b00

GUTS_DEVDISR2 0x00000000

Our board:

GUTS_DEVDISR1 0x03403b00

GUTS_DEVDISR2 0x00000000

The difference is the SEC configration.

P1010RDB:  SEC       bits[  7:7  ] = 0 SEC4.4 enable

Our board :   SEC       bits[  7:7  ] = 1 SEC4.4 disable

Thank you again for your help.

[ufedor]

Please check whether IFC registers are writable on the problem board.

Compare LAW registers dumps on both boards.

[ufedor]

Please compare values of the GUTS_DEVDISR1 for both boards.