What is the slowest SPI CLK for P2020?

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What is the slowest SPI CLK for P2020?

Contributor I

Is my calculation correct? Assume the system clock is 100MHz, and its 1/16 is selected as the input clock to eSPI Baud rate generator. PM is set to the max value of 15, then the SPI clock will be 100M/16/(2*(15+1))=0.195M.


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NXP TechSupport
NXP TechSupport

SPI minimum clock frequency estimation:

a) SPI module input clock is platform clock divided by two.
b) the SPI module input clock may be pre-divided by /16 by setting DIV16n bit in ESPI_SPMODEn register.
c) this pre-divided clock is further divided by prescaler configurable by PMn field and its maximum division ratio is 32.

Resulting maximum division ratio of the platform clock is /2/16/32 = 1024.
Minimum supported CCB frequency is 266 Mhz, so minimum SPI clock frequency is 260 kHz.

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