Using Watchdog Interrupt with MPIC in P4080

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Using Watchdog Interrupt with MPIC in P4080

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clemensreibetan
Contributor I

Hi,

I still struggle to get a watchdog interrupt in P4080.

I want to signal to Core0 that Core4 got a watchdog timeout. I think this is possible with the MPIC.

These are the relevant setting on Core4:

TCR=0x98120000

MSR=0x2a000

MPIC_IILR1=0x0

MPIC_IIVPR1=0x88000c

MPIC_IIDR1=0x1

But when an interrupt occurs, this is what I get

Core4: MPIC_WSRSR0=0x0

Core4: TSR=0xf0000000

Core4: InterruptHandler: 0xb00 exception.

What I expected was that there is something in the MPIC_WSRSR0.

I also set EDBCR0[EDM] to 0, thanks to lunminliang, but this also didn't help.

The manual (P4080RM p. 340)

The platform indicates to the MPIC that a core watchdog timer event has occurred by

updating the core’s associated field (WRSn) in the MPIC's Watchdog Status Register

Summary Register (WSRSR).

So what else do I need to do so the WSRSR is updated?

Thanks for the help so far.

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lunminliang
NXP Employee
NXP Employee

Hi,

I thinks two things need to make clear:

1.  "Core4: InterruptHandler: 0xb00 exception."

    >>Make sure if this is Watchdog? If there is any interrupt on Core0?

2.  "But when an interrupt occurs, this is what I get

    Core4: MPIC_WSRSR0=0x0

    Core4: TSR=0xf0000000"

    >>Do you get before or after the interrupt execution?


Have a great day,
Lunmin

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scottwood
NXP Employee
NXP Employee

The watchdog expirations come in phases.  On the first expiration, TSR[ENW] is set and no interrupt happens.  On the second, TSR[WIS] is set, and a watchdog exception (not the MPIC interrupt) happens if TCR[WIE] is set.  On the third expiration, the action in TCR[WRC] takes place (in your case, causing an MPIC interrupt).

Since you have TSR[WIS] set, you will get that exception one watchdog period before the MPIC interrupt.  I'm guessing that "0xb00 exception" is the watchdog exception but I don't know how you've programmed that IVOR.

108 Views
clemensreibetan
Contributor I

Yes indeed that was my problem. I thought it would set the MPIC interrupt when the interrupt in the core is set.

Now I just disabled the interrupt (TCR[WIE]=0) and it kinda works.

Now I get the external interrupt on the other core exatctly 1 time.

I handle this with this routine:

// read IACK

value = *((unsigned long *)(0xFE000000 + 0x400A0));

// clear Watchdog status register

*((unsigned long *)(0xFE000000 + 0x43A00)) = 0x100;//3 << 8;

//disable external interrupt

asm("wrtee %0" : : "r" (0));

// clear EOI

*((unsigned long *)(0xFE000000 + 0x400B0)) = 0;

// check EOI

value = *((unsigned long *)(0xFE000000 + 0x400B0));

if (value)

{

     printf("Core0: EOI=0x%x\n\r", value);

}

// reenable external interrupts

asm("wrtee %0" : : "r" (1));

After this I reset the TSR to 0x0 and wait till it is 0xd0000000 (Watchdog expired for the 3rd time). But now the MPIC_WSRSR0 is not set anymore.

Why not? (I am using the mixed mode of the MPIC)

Hope you can help me with this.

Thanks for the help up to now.

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