We have a target based on P1022.
IRQ6 line of Processor is connected to CPLD. Line is pulled up by default.
Observation 1 : This line is being driven high permanently from CPLD. Still there are spurious interrupts seen on IRQ6 line in processor which are also increasing in a random manner. Interrupt is edge triggered (high to low)
Observation 2 : To track the status of line internally. We configured the interrupt line as input in CPLD. Still there were spurious interrupts seen in Processor but we did not detect any change in digital level input of this line in CPLD. No change from 1 to 0 was triggered in CPLD. CPLD always received the line as high input.
The device tree node configuration for corresponding interrupt is -
interrupt-parent = <&mpic>;
interrupts = <6 3 0 0>;
Please suggest to identify the issue.
To disable interrupt from an external PCIe device it is needed to refer to the device documentation.
Value of PIC_EIVPR6 is 0x80006
I will update the rest of query in my subsequent reply.
Please provide value of the PIC_EIVPR6.
Please use a digital scope and capture trace of the IRQ6 pin voltage behaviour.
Isn't the IRQ6 shared with PCI Express 2 INTC?
Refer to the P1022 QorIQ Integrated Processor Reference Manual, 10.4.6 PCI Express INTx/IRQn sharing.