Unmask Internal Interrupt in the MPIC in P4080

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Unmask Internal Interrupt in the MPIC in P4080

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clemensreibetan
Contributor I

Hi all,

I have a problem using the MPIC on the P4080.

I cant unmask the internal interrupt 1.

When I do the following:

const uint32_t MPIC_IIVPR1 = 0x40000 + 0x10200 + 32*1;

uint32_t value = (8<<(31-15)) | (1) & ~(1 << 31);

cout << "value=" << hex << value << "\n\r";

*((uint32_t *)(CCSRBAR + MPIC_IIVPR1)) = value;

cout << "MPIC_IIVPR1=" << *((uint32_t *)(CCSRBAR + MPIC_IIVPR1)) << "\n\r";

I get as output

value=80001

MPIC_IIVPR1=880001

That means the interrupt is masked (P4080RM.pdf p. 1699). Why does this happen and what do I have to do to unmask it?

And am I right that if a watchdog interrupt in a core appears, the corresponding bit in the MPIC_WSRSR0 (Watchdog status register) should be set? What else do I have to do to see watchdog interrupt in other cores?

Thanks in advance.

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3 Replies

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lunminliang
NXP Employee
NXP Employee

Hi,

1. Do you get MPIC_IIVPR1 "0x00880001"? If so MSK is 0, the corresponding interrupt is unmask as the reference manual.  My document version is Rev 2, 05/2014 by the way.

2. If any of the WRSn bits in WSRSR are set (essentially ORing all watchdog timer expiration events), an internal interrupt is generated.


Have a great day,
Lunmin

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clemensreibetan
Contributor I

Oh my.... of course you are right! It was late yesterday, sorry for this stupid question.

And thanks for the fast reply.

But to the second one I still have a question.

What do I need to do so a bit in the WSRSR gets set?

Shouldn't they be set if a watchdog interrupt in a core occurs? What settings do I need, so a watchdog interrupt in a core sets the bit in the WSRSR?

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clemensreibetan
Contributor I

OK I think I know where my problem is.

These are the settings that I try:

TCR=0x98100000

MSR=0x2a000

MPIC_IILR1=0x0

MPIC_IIVPR1=0x880001

MPIC_IIDR1=0x1

DBCR0=0x80000000

And when an watchdog interrupt occurs this is what I get:

Watchdog status=0x0

TSR=0xc0000000

Core4: InterruptHandler: 0xb00 exception.

The Problem here I think is that EDBCR0[EDM] = 1 which is not what I want because the manual says that:

There are four different actions taken in response to such a watchdog timer expiration

depending on the value programmed in TCR[WRC] and EDBCR0[EDM] of the core:

• The platform indicates to the MPIC that a core watchdog timer event has occurred

for WRC/WRS==01 while EDM core output == 0

• The platform indicates to the MPIC that a core watchdog timer event has occurred

and automatic reset of that core for WRC/WRS==11 while EDM core output == 0

• The platform indicates to the MPIC that a core watchdog timer event has occurred

and device output RESET_REQ_B is asserted to external world: WRC/WRS==10

while EDM core output == 0

• SoC-specific debug action taken when WRC/WRS==01, 10, 11 while EDM core

output == 1.

So what I want is the first thing. But how do I change EDBCR0[EDM]? And will the watchdog interrupt then be visible to other cores?

It would be nice if someone could help me with this.

P.S. I'm using a Codewarrior TAP to program the P4080.

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