Uboot problem on uncustom P2020RDB-PC board

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Uboot problem on uncustom P2020RDB-PC board

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huyang
Contributor III

Hi all,

We have an uncustom P2020RDB-PC board.

The differences from our board to custom P2020RDB-PC borad are:

1. we have 4GB DDR3 instead of 1GB DDR3 on custom board;

2. we have 64MB NOR Flash instead of 16MB NOR Flash on custom board.

And we built a 36-bit uboot and modified relevant uboot source code, as below:

#define CONFIG_SYS_TEXT_BASE 0xeff80000-------->0xfeff80000
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc---------->0xfeffffffc
#define CONFIG_SYS_CCSRBAR 0xffe00000------------>0xffe00000

#define CONFIG_SYS_SDRAM_SIZE_LAWLAW_SIZE_1G------->LAW_SIZE_4G
#define CONFIG_CHIP_SELECTS_PER_CTRL1-------->2
#define CONFIG_SYS_MAX_FLASH_SECT128------>512

#define CONFIG_SYS_FLASH_BASE  0xef000000--------->0xec000000

We flash the uboot to the last 512kbit on NOR Flash, and when we boot the board, uboot printing msg as below:


U-Boot 2013.10 (Jun 19 2014 - 17:42:04)

CPU0:  P2020E, Version: 2.1, (0x80ea0021)
Core:  e500, Version: 5.1, (0x80211051)
Clock Configuration:
CPU0:1200 MHz, CPU1:1200 MHz,
CCB:600  MHz,
DDR:400  MHz (800 MT/s data rate) (Asynchronous), LBC:37.500 MHz
L1:    D-cache 32 KiB enabled
I-cache 32 KiB enabled
Board: MYP2020RDB CPLD: V4.1 PCBA: V4.0
rom_loc: nor upper bank
SD/MMC : 4-bit Mode
eSPI : Enabled                                                                 
I2C:   ready
SPI:   ready
DRAM:  DIMM 0: is not a DDR3 SPD.                                              
SPD error on controller 0! Trying fallback to raw timing calculation           
Detected UDIMM Fixed DDR on board
1 GiB (DDR3, 64-bit, CL=6, ECC off)        


And it stuck here, the DDR3 information shown in msg is still 1GB.

Is there any possible reason for this?

Is this a SPD problem or is there anything we missed when we modify the uboot.

We are looking forward to your advise.

Best Regards,

Hu      

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8 Replies

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scottwood
NXP Employee
NXP Employee

Yes, it's an SPD error as the message says.  The "is not a DDR3 SPD" message is printed by ddr_compute_dimm_parameters() in drivers/ddr/fsl/ddr3_dimm_params.c, when finding a memory type other than SPD_MEMTYPE_DDR3.  Assuming this actually is DDR3, either the SPD is incorrect, or something is going wrong when reading it.

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敏赵
Contributor I

Hi,

I have the same problem with Hu.

We can boot the uboot on custom p2020rdb-pc board even if we had no spd files in eeprom.

(We used default setting for the p2020rdb-pc board to make uboot, and  u-boot verison is 2013-10. )

Now we change DDR3 to SAMSUNG K4B8G1646B(1 GB *4) instead of original chips on p2020rdb-pc.

We used the same version of uboot(2013.10) and just modify some address value like Hu did.

When we boot the uboot, the printing msg was just like to Hu's.

 

Did it mean that uboot have made relevant configurations that match DDR3 on custom p2020rdb-pc, so even without spd files it still can work.

But when we change the DDR3 chips, the configurations did not match, so it hang there.


Then which files in uboot should I modify that can make my DDR3 work?

Looking forward to your reply.

Best regards,

Min Zhao

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adeel
Contributor III

Hi,

You need to create one DRAM config file specific for your DRAM. Also, a c file where you can specify its size and initialization routines. Refer to sample dram initialization source file in u-boot code. This initialization must be done from Flash memory before the code jumps to DRAM.

Regards,

Adeel

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huyang
Contributor III

Thanks for your reply.

1. Now, we don't have a spd in eeprom.

Since is not a custom board, we don't have a spd file that match our DDR3(Our DDR3: 4 chips of K4B8G1646B-MCK0).

Where should we found the spd file, and how can we flash it to the eeprom?

2. We used custom P2020RDB-PC board before.

We got same problem there, but we can boot the uboot even we got no spd files in eeprom.

At that time, the printing log as below:

CPU0: P2020, Version: 2.1, (0x80e20021) 

Core: E500, Version: 5.1, (0x80211051) 

Clock Configuration:

  CPU0:1000 MHz, CPU1:1000 MHz, 

  CCB:500 MHz,

  DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:50 MHz 

L1: D-cache 32 kB enabled

  I-cache 32 kB enabled

Board: P2020RDB-PCA CPLD: V4.1 PCBA: V4.0 

Error reading i2c boot information! 

I2C: ready

SPI: ready

DRAM: DDR: failed to read SPD from address 82 

SPD error on controller 0! Trying fallback to raw timing calculation 

Detected UDIMM Fixed DDR on board

1 GiB (DDR3, 64-bit, CL=5, ECC off)

Flash: 16 MiB

L2: 512 KB enabled

NAND: 32 MiB 

MMC:  FSL_SDHC: 0                                                            

PCIe1: Root Complex of mini PCIe SLOT, no link, regs @ 0xffe0a000            

PCIe1: Bus 00 - 00

PCIe2: Root Complex of PCIe SLOT, x1, regs @ 0xffe09000                      

  02:00.0    - 1095:3132 - Mass storage controller                          

PCIe2: Bus 01 - 02

In:    serial

Out:  serial                                                                

Err:  serial

Net:  eTSEC2 is in sgmii mode.

uploading VSC7385 microcode from ef000000                                    

PHY reset timed out

eTSEC1, eTSEC2, eTSEC3

Hit any key to stop autoboot:  0


Why the custom board can work without spd files and now we can't?

We are looking forward to your reply.


Regards,

Hu

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yipingwang
NXP TechSupport
NXP TechSupport

On P2020RDB-PC, the on-board EEPROM is used to store SPD data, if case of absence or corrupted SPD, falling back to timing data embedded in the source code will be used, Raw timing data is extracted from DDR ship datasheet, please refer to the source file board/freescale/p1_p2_rdb_pc/ddr.c.

Also please refer to "DDR Setup" section in the header file include/configs/p1_p2_rdb_pc.h for some basic configurations adjustment, for example LAW size.

In addition, if there is no SPD on your target, you could disable SPD(CONFIG_DDR_SPD) in p1_p2_rdb_pc.h and use "Default settings for DDR3"(defined in header file) to configure DDR controller instead.  You could use QCS tool to assist you to determine these parameters according to your target, QCS can be downloaded from PE_QORIQ_SUITE: Processor Expert Software: QorIQ Configuration Suite.

Thanks,

Yiping

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huyang
Contributor III

Hi Yiping,

Thanks for your reply.

Now, we already got spd files for our new DDR3 chips.

But we can't get into uboot, is there a way that we can flash spd file into EEPROM through Codewarrior?

Looking forward to your reply.

Regards,

Hu

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yipingwang
NXP TechSupport
NXP TechSupport

Hello Hu,

CodeWarrior doesn't provide direct support to flash I2C EEPROM. You could design a CodeWarrior bare board project to write I2C.

I attached a sample source file for you.

In addition, you also could configure DDR raw timing in u-boot, and boot up u-boot, then write SPD with i2c command under u-boot prompt.

If further assistance is needed, please feel free to let me know.


Have a great day,
Yiping Wang

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敏赵
Contributor I

How should I design the project to write I2C?

First, is it same to build a p2020rdb-pc project when build the project for I2C?

Second, should I replace all .h and .c file with you supplied, and delete the .tcl file?

Third, how should I flash I2C EEPROM?

Thanks a lot.

Best regards

Min Zhao

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