The problem of DDR on uncustom P2020RDB-PC

[敏赵]

Hi，

We designed a target board using p2020 CPU referring to the design of P2020RDB-PC.

We have 4G DDR. Following is the u-boot print message:

We modified the configurations of DDR in p1_p2_rdb_pc.h, like this:

#define CONFIG_SYS_DDR_CS0_BNDS     0x0000007f

#define CONFIG_SYS_DDR_CS0_CONFIG   0x80014402

#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000   

#define CONFIG_SYS_DDR_CS1_BNDS     0x008000ff

#define CONFIG_SYS_DDR_CS1_CONFIG   0x80014402

#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000

We also modified the configurations of DDR in ddr.c, like this:

	.n_ranks = 2,
	rank_density =2147483648u,
	capacity = 4294967296u,

Why it print 2G left unmapped? We have modify the configurations of DDR refering to DDR datasheet. But it still stuck in DDR.

Did I need to modify more files?

Thanks a lot.

Best regards,

Min Zhao

[scottwood]

U-Boot never maps more than 2 GiB for its own use, since there is only 4 GiB of effective address space, and some needs to be used for I/O.  This extra memory will still be available to an OS launched by U-Boot.

When you say "still stuck in DDR", do you mean that U-Boot hangs at that point?  Since it appears you're not using SPD to configure DDR, be sure that all of the other register settings (e.g. timings) are set correctly for your RAM.

[baijack]

We tried to modify these follow registers in the file named p1_p2_rdb_pc.h:

**************************************************************************************

/* Default settings for DDR3 */

#ifndef CONFIG_P2020RDB

#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f

#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302

#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000

#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f

#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302

#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000

#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef

#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000

#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000

#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000

#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600

#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608

#define CONFIG_SYS_DDR_SR_CNTR 0x00000000

#define CONFIG_SYS_DDR_RCW_1 0x00000000

#define CONFIG_SYS_DDR_RCW_2 0x00000000

#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */

#define CONFIG_SYS_DDR_CONTROL_2 0x04401050

#define CONFIG_SYS_DDR_TIMING_4 0x00220001

#define CONFIG_SYS_DDR_TIMING_5 0x03402400

#define CONFIG_SYS_DDR_TIMING_3 0x00020000

#define CONFIG_SYS_DDR_TIMING_0 0x00330004

#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846

#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF

#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000

#define CONFIG_SYS_DDR_MODE_1 0x40461520

#define CONFIG_SYS_DDR_MODE_2 0x8000c000

#define CONFIG_SYS_DDR_INTERVAL 0x0C300000

#endif

**************************************************************************************

The model of DDR3 is K4B8G1646B-MK0 from Samsung. The attarch is the datasheet of it.

My question are as follows:

Firstly,for these above registers, whitch registers is must modified for matching our 4GB DDR3 and how to modify?

Secondly,except for these above registers, whitch another registers need i have to modify?

We are looking forward to your reply.

Thank you very much.

Bai Jack

[yipingwang]

Hello Jack,

Please refer to the file board/freescale/p1_p2_rdb_pc/ddr.c, the above DDR controller micros are used in the function fixed_sdram.

Also please refer to the following code in arch/powerpc/cpu/mpc85xx/cpu.c

#if	defined(CONFIG_SPD_EEPROM)	|| \
	defined(CONFIG_DDR_SPD)	|| \
	defined(CONFIG_SYS_DDR_RAW_TIMING)
	dram_size = fsl_ddr_sdram();

#else

dram_size = fixed_sdram();

#endif

So in order to use the DDR controller configuration in p1_p2_rdb_pc.h, you need to disable some specific micros as mentioned in the above code.

About these DDR controller configuration parameters, you could download and install QCS tool to assist you.

Previously I sent you a CodeWarrior project to write I2C SPD through email, actually you could use you DDR SPD file directly without modifying these parameters.

Thanks,

Yiping

[敏赵]

Our memory map is：

0x00000000 ~ 0xffffffff    DDR

oxfec000000 ~ 0xfefffffff  NOR

0xff8f80000 ~ 0xff8ffffff  L2 SRAM

0xfffe00000 ~ 0xfffefffff  CCSR

We use 36-bit. How should I modify the u-boot codes to assign 4GB memory addresses to DDR?

Yes, our u-boot hangs at that point. We have set the DDR configurations based on out target DDR datasheet. And we modify the configurations of DDR in ddr.c.

Now I try to use SPD to configure our DDR, we have modify relevant variables in ddr3_dimm_params.c, which defined by dimm_params_t ddr_raw_timing = {} in ddr.c

But it still hangs at that point. Do I need modify other configurations?

Best regards,

Min Zhao