TLB1 IPROT bit with a PCIe IO memory space?

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TLB1 IPROT bit with a PCIe IO memory space?

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sopgenorth
Contributor II

Does it make sense to use the invalidate protection (IPROT) bit for an entry that also has the cache-inhibited and guarded bits set?

It seems like there would be no need to have 'invalidate protection' enabled when cache-inhibited is also enabled since I would imagine there would be no entries for it in cache anyway. 

This is on a p1014 and p2010 CPU, trying to get the correct TLB entries for a PCIe IO memory space. With the IPROT bit disabled, the CPU crashes ~5% of the time on reboots (machine check exception, producing a BUS_RBERR or read data bus error). With the IPROT bit enabled the CPU no longer appears to crash. 

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r8070z
NXP Employee
NXP Employee


Have a great day,

Yes it makes sense to use the invalidate protection (IPROT) bit for an TLB entry that also has the cache-inhibited and guarded bits set. If IPROT is set, this entry is protected against invalidation due to TLB invalidate command. This command does not care what type of memory page is described by this TLB entry. It simply marks TLB entry as invalid. Check the processor errata for problem related to the IPROT bit and TLB flash invalidate.

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393 Views
r8070z
NXP Employee
NXP Employee


Have a great day,

Yes it makes sense to use the invalidate protection (IPROT) bit for an TLB entry that also has the cache-inhibited and guarded bits set. If IPROT is set, this entry is protected against invalidation due to TLB invalidate command. This command does not care what type of memory page is described by this TLB entry. It simply marks TLB entry as invalid. Check the processor errata for problem related to the IPROT bit and TLB flash invalidate.

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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