Regarding HRESET issue for P1020...

[pankajpandey]

Hi,

In my board i m not using CPLD for p1020 POR settings.My SYSCLK is 66.6MHz.

I m facing one issue in Power on Reset for P1020 controller.

When Board Power up P1020 controller dont start executing code unless i give manual Reset using Switch(SW2).

I measured the Rise time/Fall time of HRESET its around 150usec.

Pillup value on HRESET is 10k and Decap of 0.1uF.

On eval board Power on reset goes to CPLD and CPLD generates HRESET of 10nsec Rise time.

Is this condition critical for boot up of P1020?

How can i implement this fast rise time for HRESET without using CPLD?

Regards,

Pankaj

[andrei_skok · Accepted solution]

According to the P1020 Datasheet, Table 5. RESET Initialization Timing Specifications,

Required assertion time of HRESET - 25 usec minimum

Maximum rise/fall time of HRESET - 1 SYSCLK = 15 nsec maximum

That means you have to keep HRESET low for 25 usec minimum and then drive it high with the rise time 15 nsec maximum. It is not possible to do this using just resistor and capacitor. You have to use a CPLD or any equivalent circuit.

[lunminliang]

On P1020 Hardware Specifications, the maximum rise/fall time of HRESET is one SYSCLK, for your case, it's about 15ns.

You can verfify this by measuring the rise/fall time when you give manual reset, if it's less than 15ns, then it's the problem, if not, you can comparing the two signal for the difference.

To reduce the rise time, maybe you can reduce pullup resistor and decoup( I am not an expert on this), how did you design your reset circuit?