QorIQ P4080 ELBC - how to configure GPCM /OR/BR/CS/LAW under UBOOT

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QorIQ P4080 ELBC - how to configure GPCM /OR/BR/CS/LAW under UBOOT

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sam_lee
Contributor II

Hi Expert,

 

I would like to connect a FPGA to the ELBC of P4080, and then access the FPGA from Linux BSP via P4080 ELBC.  

There some simple questions against the configurations under UBOOT. Could you please share if there any experience? Any comments would be appreciated.

1, how to configure the GPCM Mode for the ELBC of P4080

2, how to configure the OR/BR register (for example OR4, BR4)

3, how to configure the CS (for example CS4, CS5)

4, are there any more registers which I need to configure?

 

Regards,

Sam

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3 Replies

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alexander_yakov
NXP Employee
NXP Employee

1. ELBC supports several modes of operation (chip select machines) - GPCM, FCM and UPM. MAchine is selected by ORn[MSEL] field. Please look P4080 Reference Manual, Section 13.1.3 for details.

2. ORn/BRn register pair for GPCM mode should be configured as described in Sections 13.3.5 and 13.3.6

3. CS line is configured by setting values to appropriate ORn/BRn register pair, where n is CS line number. For CS4 you should configure BR4/OR4.

4. GPCM has very small amount of configuration parameters, most of them are configured in ORn/BRn register pair. In addition you may look to eLBC_LBCR and eLBC_LCRR if necessary.

P4080 Reference Manual is available from P4080 product page, "Documentation" tab:

https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/qoriq-platforms...


Have a great day,
Alexander
TIC

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sam_lee
Contributor II

Thanks Alexander,

One quick question, could you please share an example regarding how to enable CS4 by configuring OR4/BR4?

Regards,

Sam

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alexander_yakov
NXP Employee
NXP Employee

Example base address 0xFFDF0000, memory size 1MB,  8-bit data bus, GPCM, Valid
BR4 = 0xffdf0801
OR4 = 0xffff8ff7

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