Problems about P2020 in sleep mode

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Problems about P2020 in sleep mode

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huyang
Contributor III

Our new design uses QorIQ P2020, and the Hardware design is based on P2020RDB.

Now after we power on, we can't connect our board with jtag, the debug tool is USB TAP and CodeWarrior 10.3. (We use USB TAP on P2020RDB-PCA before, and it's ok.)

And we found that asleep pin is high, asleep led is on.

Is that mean our P2020 in sleep mode after we power on?

or Is there any clue that help us locate where the problem is?

Thanks.

B.R.

Hu Yang

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hwrobel
NXP Employee
NXP Employee

Check all(!) pins that are listed in our EC document with any special footnote.

Also check that your part symbol maps all(!) GND and power pins correctly.

If the chip stays “ASLEEP” right on power up, it usually points to an incorrect configuration at reset time.

Usually one or more of the pins are incorrectly terminated or pulled by external components.

This involves all(!) pins with a footnote, not just the standard pins with cfg_ function.

Hope this helps,

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huyang
Contributor III

Hi. Thanks for your reply.

We checked all pins that listed in our EC document with special footnote.

And we found some POR resistor related to pll ratios did not populate. They are cfg_sys_pll[0:2], cfg_ddr_pll[0:2], cfg_core0_pll[0:2], cfg_core1_pll[0:2].

And we checked these information in P2020 Reference Manuel, it gives us some options.

Do these radios only affect the speed of CPU and DDR, or only some correct choice can make the board work.

Can you give us some advise about how to choose the pll radios?  Or we can choose any radio we want?

Thanks.

Regards,

Hu Yang

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hwrobel
NXP Employee
NXP Employee

Please consult the RM in conjunction with AN4261 to determine the correct settings for all pins.

Note that you need to stay within the limits defined by the EC document for your specific chip in question of course.

Hope this helps,

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huyang
Contributor III

Hi Heinz,

Thanks for your reply.

We have checked all the pins that mentioned in P2020EC and AN4261.

Here we have some problem with MCK[0:5], it says in document "all unused MCK pins must be disabled via DDRCLKDR register".

However, we couldn't found any pins that correspond to bits in DDRCLKDR register. So how can we change the value of DDRCLKDR


And we found some pins such as USB_NXT, USB_DIR, USB_D[0:7],SDHC_DATA[0:7], SD_RX[0:3],  pins like that we don't used, the checklist said when pin not used it should connect through 1k Ω GND or pull high through resistor.

But we just left floating, could this cause the problem we have?

Thanks.

Regrads,

Hu

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