PCI Express Read Burst Transaction

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PCI Express Read Burst Transaction

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Contributor III

Question regarding initiate burst PCI Express transaction from Host CPU .(Using p1022).

As far as I understand CPU access to PCI memory will end-up in a 32bit or 64bit PCIE transfer requests.

Is it possible to create a read transaction of more then 64 bit (that  will be implemented in one burst on the PCI Express)?

Is it possible to accomplish that with the DMA Controller where source address will point to a PCIE memory space?

Micha

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NXP TechSupport
NXP TechSupport

Your understanding is correct - it is possible to initiate PCIe transfers having data payload more than 64 bytes using DMA.

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NXP TechSupport
NXP TechSupport

Your understanding is correct - it is possible to initiate PCIe transfers having data payload more than 64 bytes using DMA.

View solution in original post

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Contributor II

@ufedor @Micha_Yardeny

I'm using an LS1012A as an Endpoint and need to read large amounts of data from an RC. Performing memory-mapped reads using the core is working but extremely slow. I assume this is because the MRd TLPs are very small. Can you point me to any code examples showing the use of eDMA with PCIe, or even just a basic overview of how to achieve burst transactions?

Thanks,

Brett S.

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Contributor III

Basically We have now that DMA working fine with 128 bytes payloads above PCI-E .

Can we theoretically increase DMA transfer size beyond the MPS (Maximum Payload Size)

Or in other works my question is can the host splits DMA transection to smaller TLP packets ?

If the answer is negative is that possible to go around it with limiting DMA band width  BWC.?

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NXP TechSupport
NXP TechSupport

The split size in the described case is equal to the BWC (if BWC is less or equal to negotiated payload size).

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Contributor III

Thanks and if BWC is disabled would the DMA split the transaction to maximum payload size TLP's? 

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NXP TechSupport
NXP TechSupport

Correct.