P5020 LTSSM states

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P5020 LTSSM states

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kyleb
Contributor I

Hello, Table 18-4 of the P5020 RM lists there as being five different Disabled states in the LTSSM State Status Register, Disabled through Disabled(4). What is the difference between these states? In particular, Disabled(1) and Disabled(4)? I am currently using the P5020 as a host for two end points, an x4 on PCIe Controller 1 (working) and an x1 on PCIe Controller 2. For the non-working Controller 2, I see the LTSSM stall out in either Disabled(1) or Disabled(4). However, I also see the working Controller 1 go into Disabled(1) before making it to the expected L0 state, so this Disabled state appears to be part of the link process which I was not expecting.

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ufedor
NXP Employee
NXP Employee

A PCIe lane training process is a complicated sequence performed by SerDes hardware microcode.

Because the training is performed without software control, there is no publicly-available document describing the microcode operation.

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