P4080DS virtual address or physical address?

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P4080DS virtual address or physical address?

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peterzheng
Contributor II

Hi,

I am currently doing a project which tries to partition the memory space and CPC cache of P4080DS. To achieve this goal, I used two approach:

(1) Modify the hypervisor device tree

(2) Configure the LAW registers and Partition Control Registers of P4080DS

There are some questions that I am a bit confused about the memory mapping of P4080DS:

(1) The base address specified by LAW, are they physical address or virtual address?

(2) If the address specified in LAW registers are physical address, how can Partition Control Register decide the allocation of CPC ways to LAW? Because I thought that the connection between DDR and cache is fixed.

(3) When I was editing the hypervisor device tree, I tried to partition the CPC by adding the allocate-cpc-ways property in physical memory node. Here the pma node, are they refers to physical memory area? Is the address of it physical address?

(4) If the address in PMA is physical memory, same as question (2), how does this achieved?

Regards,

Peter Zheng

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LPP
NXP TechSupport
NXP TechSupport

1. LAW base address is a physical address. Virtual addresses are local to the core. Core's MMU performs virtual to physical address translation. So, the SOC hardware never deals with virtual addresses.

2.

Partition ID equates to the CSD_ID assigned by the LAWs.

A CPCPIRn register with PID bit set that matches access CSD_ID will control CPC way allocation via CPCRn register. 

3.

A PMA is defined with the true physical address (must be size aligned)

By default the Corenet platform cache (CPC) allocates all ways to all PMAs. If the allocate-cpc-ways property is specified for a PMA, the selected ways will be removed from the default pool of ways (used by all other PMAs) and only access to the PMAs that specifically reference the ways (using the allocate-cpc-ways property) will allocate from them.

4.

TLBs translate a virtual address to a physical address (M bit is set to allow memory coherency).

The physical address hits a LAW. The LAW assignes the target ID (e.g. DDR) and CSD_ID.

CSD_ID is used to match bits in CPC Partition Control Registers CPCPIRn.


Have a great day,
Pavel

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peterzheng
Contributor II

Hi Pavel,

Thank you for your reply. Given your explanations, I still have some points not very clear.

(1) Could you refer to the document which mentioned that the LAW Base address is physical address?

(2) From my understanding, the connecting from memory to cache is fixed in the hardware in most processor, which means the mapping of physical address to cache is fixed. In this case, if the LAW specifies the physical address. How can we change the connection from physical memory to CPC? Is it because the CoreNet Fabric has the capacity to do this? Point out if my understanding was wrong.

Thank you for your help.


Regards,

Peter Zheng

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