P4080 PCIe Flash vbank clarification

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P4080 PCIe Flash vbank clarification

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Contributor III

My problem comes from absence of detailed hardware specification for P4080 PCIe board, also known as Niagara 710.

So I can only guess how did they implement Flash virtual bank switching.

From brief hardware specification I know that there is 1Gb NOR Flash on board.

In documentation it is suggested to put all experimental images to  vBank4

So, being booted from vBank0 we see:

0xEBF8_0000    <- address to place uBoot image (vBank4)

......

0xEBFF_FFFc    <-  address to start execution from (vBank4)

---------------------------------

0xEC00_0000     <-   address to place RCW. (vBank4)

Then  $>n710_reset altbank do some magic and the following translation should happen

Address:

0xEC00_0000 should translate to 0x0000_0000

0xEBF8_0000 -//- to 0xFFF8_0000

Basically we need to translate 0xEC to 0x00 and 0xEB to 0xFF, but can't imagine a simple circuit to perform such translation.

My another problem is about uBoot image size. It should be constant to keep recommended placement address valid.

Else we have a real chance to miss expected boot vector location.

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NXP Employee
NXP Employee

Hi,

Now I understand your question. Basically, however will be the configuration (cfg1 or cfg 2..) these addresses is what you see when you program the u-boot & RCW (after the flash is proper initialized - TLB, LAW, eLBC and so on are set up correctly).

When the processor is booting up, based on boot location (the cfg_rom_loc and RCW location are driven by DIP SW Settings or/and FPGA code) it can map the 4KB of code (the default TLB during booting time has 4KB).

The e500mc core boot start address(0xFFFF_FFFC) will point to the end of CS0 Flash due to OR0[AM]=0. In this phase, the core is using the relative addressing.

After you change the BR0,OR0, you can use absolute addressing.

Keep in mind, the bootloader is placed to the end of CS0, and the RCW is placed to the start of CS0.

Just for your info -> in our nomenclature a CS0 (ChipSelect 0) refers to BR0 and OR0's pair (used for setting up the eLBC controller).

When the chip starts execution, the boot vector is mapped at 0xfffffffc.  The boot code then changes the flash mapping (with an interim state where it's mapped repeatedly throughout the address space) before it runs any code that depends on the link address.

You can take a look in the P4080 Reference Manul also. Quote from manual - Boot Space Translation - chapter 4.3.1.3

"When each core comes out of reset, its MMU has one 4-Kbyte page defined at 0x0_FFFF_Fnnn. Each core begins execution with the instruction at effective address 0x0_FFFF_FFFC. To get this instruction, the core's first instruction fetch is a burst read of boot code from effective address 0x0_FFFF_FFE0. For systems in which the boot code resides at a different address, the device provides boot space translation capability. Note that boot space translation affects transactions initiated by all cores in the same manner".

So, like a conclusion this is processor/hardware capability to fetch the booting code according with RCW and DIP SW settings.

Regards,

Marius

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3 Replies
167 Views
NXP Employee
NXP Employee

Hi,

I haven't worked with P4080PCI yet, but as far I know it has the same flashes (NOR, NAND and SPI) as P4080DS.

So, basically you can use the information from P4080DS, regarding the virtual banks (because is the same processor).

The flash address range is 0xE8000000 - 0xEFFFFFFF.

Each flash sector is 128KB and there are 1024 sectors for a total of 128MB of NOR flash space.

The flash space is further divided into 8 virtual banks.

_________

|Bank7 | <----- RCW for the u-boot at Bank 0 is in this bank at address 0xe8000000

|Bank6 |

|Bank5 |

|Bank4 |

|Bank3 |

|Bank2 |

|Bank1 |

|Bank0 | <----- Bank 0 starts at 0xef000000; u-boot at address 0xeff80000 in this bank

---------

For P4080DS changing SW7[1:4] swaps the banks. Adjust SW7[1:4] to the bank number you want to use.

By default Bank 0 is used (SW7[1:4] = 0000). This means bootcode will is always NOR Flash Bank 0,

and the RCW is at Bank 7 (address 0xe8000000).

RCW for Bank i is in Bank (7-i)

You should find a similar SW for P4080PCI (only if you want to change the default behavior).

Regarding the u-boot binary size this should have 512KB most of the time. However is the size, it's always mandatory to write the u-boot binary in the last 512KB of the NOR flash.

Regards,

Marius

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Contributor III

For P4080PCIe board only 2 banks can be altered Bank0 (Cfg1) <-> Bank4 (Cfg2)

So the picture is like following:

_________

|Bank7 | <----- (Cfg1) RCW for the u-boot at Bank 0 is in this bank at address 0xe8000000

|Bank6 |

|Bank5 |

|Bank4 | <-- (Cfg2) Bank4  starts at 0xeb00_0000; u-boot image aligned to bottom of the bank (should start @0xebf8_0000)

|Bank3 | <-- (Cfg2) RCW for Bank4 @ 0xec00_0000 (7-4 = 3)

|Bank2 |

|Bank1 |

|Bank0 | <----- (Cfg1) Bank 0 starts at 0xef000000; u-boot at address 0xeff80000 in this bank

---------


This picture explains recipes given in documentation very well, but it's still unclear how Bank4 bottom instruction at address 0xebff_fffc translate to address 0xffff_fffc from which CPU core starts to execute.

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168 Views
NXP Employee
NXP Employee

Hi,

Now I understand your question. Basically, however will be the configuration (cfg1 or cfg 2..) these addresses is what you see when you program the u-boot & RCW (after the flash is proper initialized - TLB, LAW, eLBC and so on are set up correctly).

When the processor is booting up, based on boot location (the cfg_rom_loc and RCW location are driven by DIP SW Settings or/and FPGA code) it can map the 4KB of code (the default TLB during booting time has 4KB).

The e500mc core boot start address(0xFFFF_FFFC) will point to the end of CS0 Flash due to OR0[AM]=0. In this phase, the core is using the relative addressing.

After you change the BR0,OR0, you can use absolute addressing.

Keep in mind, the bootloader is placed to the end of CS0, and the RCW is placed to the start of CS0.

Just for your info -> in our nomenclature a CS0 (ChipSelect 0) refers to BR0 and OR0's pair (used for setting up the eLBC controller).

When the chip starts execution, the boot vector is mapped at 0xfffffffc.  The boot code then changes the flash mapping (with an interim state where it's mapped repeatedly throughout the address space) before it runs any code that depends on the link address.

You can take a look in the P4080 Reference Manul also. Quote from manual - Boot Space Translation - chapter 4.3.1.3

"When each core comes out of reset, its MMU has one 4-Kbyte page defined at 0x0_FFFF_Fnnn. Each core begins execution with the instruction at effective address 0x0_FFFF_FFFC. To get this instruction, the core's first instruction fetch is a burst read of boot code from effective address 0x0_FFFF_FFE0. For systems in which the boot code resides at a different address, the device provides boot space translation capability. Note that boot space translation affects transactions initiated by all cores in the same manner".

So, like a conclusion this is processor/hardware capability to fetch the booting code according with RCW and DIP SW settings.

Regards,

Marius

View solution in original post