Hello NXP community,
I am running a custom board with a P3041 rev. 2.0 and U-Boot. The board has been used for a few years now with single-rank and un-mirrored dual-rank memory with 4 GB and everything works fine.
The problem now is that the memory supplier changed to mirrored dual-rank and we experienced the following problems.
U-Boot usually only uses the first 2 Gb of memory, so the error does not come up. With interleaving however, it hangs during the boot sequence. The first rank of the memory is un-mirrored at chip select 0. The second rank is mirrored at chip select 1. Both ranks are working fine with un-mirrored dual rank memory.
We also checked the SPD and the mirrored bit is set correctly. According to our JTAG test the lanes are mirrored pairwise as required by the P3041. The JTAG test also successfully uses the second bank of memory.
We are now looking for solutions to get the second rank working. The question has come up if there is a problem with the memory controller of the processor, since the configuration seems to be correct. Also our customer using the board with a custom OS states that they have read access to the second rank, but no write access. Since our tests are restricted to U-Boot we cannot test that at the moment.
I hope you guys have any idea what to do or what is going on.
Thank you very much in advance, I appreciate every help I can get.
The only point you need to check is the value of DDR_DDR_SDRAM_CFG_2[MD_EN] bit after u-boot initializes the DDR controller. It should be set to '1' in case of mirrored DIMMs. Did you check?