Hi Victor,
Some comment from application team for your information:
COREDISR prevents a core from receiving any clocks whatsoever. Boot Release Register is intended to be used to sequence when to allow a core to begin booting (so initial SoC configuration may be done with one CPU and once that is complete the others begin for example). If a CPU is disabled with COREDISR, it should never be released with BRR - that is not valid. A core which is intended never to be used should be disabled with COREDISR, as this should save a small amount of additional power compared to having its COREDISR enabled but not releasing it for booting.