P2041 e500mc MCSR[LDG] error without MCSR[LD]

[mehmetcelik]

Hi,

We are using P2041 processor and we are receiving an error MCSR[LDG] without receiving MCSR[LD]. (MCSR[LD] is 0 but MCSR[LDG] is 1). In E500mc Core Reference Manual document, it is explained why this error bit would set when LD bit is set, but there is no explanation without LD bit. MCAR, MCARU, MCSRR0 and cache address generation registers are not set either. Can you give more information why LDG bit is set when LD bit of MCSR is 0? Is there a way to get the address of error occured during the attempt if applies?

Thank you...

[ufedor · Accepted solution]

Guarded load instruction error report. Set along with LD if the load encountering the error was a guarded load (WIMGEL = xxx1xx or L1CSR2[DSPD] = 1) and that guarded load did not encounter one of the data cache errors. Set only if the error encountered by the load was an L2 or CoreNet error.

The MCSR[LDG] bit is set to indicate the machine check was taken during an guarded load instruction. This bit would be set along with the MCSR[LD] bit. This exception type is classified as an error report, and is a synchronous error. The synchronous error occurs when the instruction is ready to be completed in program order.

This error is non-maskable, the e500mc core always takes a machine check for this error report. This error indicates that an error occurred during the attempt to fetch the instruction corresponding to the address in MCSRR0 or during an attempted fetch of a younger instruction than that pointed by MCSRR0.

If a machine check is taken due to MCSR[LDG], the action that a machine check ISR should perform to dependent on the cause of the error and may or may not be recoverable. Typically, an error report error will also have an asynchronous error bit set in MCSR as well. For example, ICPERR may be a set along with LDG to indicate a L1 instruction cache parity error occurred during the instruction fetch. In this case the ICPERR is recoverable.

If recoverable, once the machine check ISR has taken appropriate action to satisfy the interrupt, the ISR should clear the MCSR[LDG] bit (write 0b1 to clear), clear any associated asynchronous MCSR bit (write 0b1 to clear), then rfmci back to the interrupted instruction. If MSR[ME=1] or MSR[GS=1], an associated asynchronous machine check may occur prior to this error report exception, and the ISR will see both an asynchronous and error event MCSR bit set. Conversely, if MSR[ME=0] and MSR[GS=0], and an exception is taken due to the error report, the ISR may also see an asynchronous MCSR bit set that would not trigger a machine check as it is masked by the MSR.