P2041 Serdes PLL could not work correct

[zhaopingyang_sg]

I use P2041 with LANE H as SGMII and Lane E/F as PCIE-2.

but when cpu bootup,I found SDRDS Register is as Follows:

|---B0RSTCTL = 0x26474507.
|---B1PLLCR0 = 0x0000000c.
|---B1PLLCR1 = 0x08000100.

it means that Serdes is reset failed.

follows is my RCW:

after this,i excute a reset sequence for SRDES,it out put as follows and reset failed at last:

-> serdes_reset
|---B0RSTCTL = 0x26474507.
|---B1PLLCR0 = 0x0000000c.
|---B1PLLCR1 = 0x08000100.
Set SD_RST
|---B0RSTCTL = 0x26474547.
|---B1PLLCR0 = 0x0000000c.
|---B1PLLCR1 = 0x08000100.
SET SDPD and PLLRST
|---B0RSTCTL = 0x26474567.
|---B1PLLCR0 = 0x0000000c.
|---B1PLLCR1 = 0x08000100.
SET RSTREQ
|---B0RSTCTL = 0x06474562.
|---B1PLLCR0 = 0x0000000c.
|---B1PLLCR1 = 0x08000100.
Clear SD_RST SDPD and PLLRST
|---B0RSTCTL = 0x06474504.
|---B1PLLCR0 = 0x0000000c.
|---B1PLLCR1 = 0x08000100.
value = 27 = 0x1b

-> serdes_dump
|---B0RSTCTL = 0x26474507.
|---B1PLLCR0 = 0x0000000c.
|---B1PLLCR1 = 0x08000100.
value = 27 = 0x1b

[ufedor]

SD_IMP_CAL_RX has to be connected through 200 Ohm to SVDD which is 1.0V only.

Provided reference clock photos show that the scope has insufficient bandwidth - the signal looks like a sinus, but it has to be digital (with sharp edges).

[zhaopingyang_sg]

follow the P2040-RM Part 3.7:SerDes PLL Reset and Reconfiguration.

I Write the SRDS1_BnRSTCTL register and read the register(B0RSTCTL /B1PLLCR0 /B1PLLCR1 ) back

Have you programmed the RCW into a Flash?

the value of RCW is read back from flash.