For peace of mind, do you see anything wrong in next clocking setup ?
K : cpu frequency (H=800, K=1000, M=1200,N=1333)
F : ddr speed = datarate in Mbps (F = 667; H=800) << mclk_freq Mhz = (333;400)
platform CCB frequency = 66.66 (sys-clk) x 6 (pll-ccb) ~ 400 Mhz
CCB-freq range for Core[1000M] : 266 Mhz min ; 533 Mhz max
core:CCB clk ratio=2.5:1
core-freq= 400 x 2.5 = 1000 Mhz
ddr3-datarate 667 Mbps is higher than ccb-clk frequency.
P2020-ddr-controller cannot be used in synchronous mode (its default mode)
use asynchronous mode : DDR-CLK-input = 66.66 Mhz
DDR: DDR-CLK ratio = 10:1 >> DDR-controller-internal-clock = 666.60 Mhz >> DDR-MCK-out=333.30 Mhz
ok, ddr3-sdram chip min freq = 303 Mhz
Par 6.1.2 DDR Clocking Range
Table 12, note-4
Asynchronous mode requirement = ok : ddr controller MCK output =333.3 Mhz is less than or equal to CCB-CLK = 400 Mhz.
I have never used ddr-controller in asynchronous mode.
Does asynchronous mode require any specific ddr-controller register-settings (timing) ?
Other question : 667Mbps datarate is higher than 400Mhz platform-ccb-clock. Does this mean that performance of P2020-cpu-core is restricted if core cannot execute instructions from on-chip caches ?
1) No, asynchronous mode does not require any special setting in the DDR controller.
2) Performance of the core is not affected. Note that the system bus supports 128-bit operations at 400MHz. Or in other words 400MHz CCB operations effectively look like 800Mhz at 64-bit bus.
Everything looks ok. What is your doubt?