[P2020] What is th core0/1 state when TRIG_OUT signal raises (using event trigger) ?

[remyritchen]

TRIG_OUT is asserted when TOSR[SEL] is non-zero and associated debugging event is triggered. READY_P0 indicate core state (ready / debug / etc) TRIG_OUT and READY_P0 are multiplexed.

When debugging event raises, what are the core state ?

- Core0 keeps in ready state ? becomes debug ?

- Concerning core1 ?

I search a mean to freeze external clocking source (RTC) for Core Time Base and Decrementer (see figure 4.7 - reference manual) when Core0 enters to debug state (thanks to debug tools). READY_P0 seems to be adapted signal but in case where event trigger is also used, what is the behavior ?

[alexander_yakov]

TRIG_OUT signal is a part of watchpoint monitor block, it may be configured to perform different functions, depending on TOSR[SEL]. The default TOSR[SEL] = 000 is "READY" function, which means "The device has completed the reset operation, and e500 core 0 is not in a powerdown (nap, doze or sleep) or debug state."

When the TOSR[SEL] is not zero, the TRIG_OUT output acts as watchpoint block TRIG_OUT output and may be used to trigger logic analyzer on several type events, depending on TOSR[SEL] value - watchpoint monitor hit, tracebuffer hit or performance monitor overflow. All these events are related to watchpoint monitor block (see Figure 24-1 in P2020 Reference Manual), and therefore, do not affect the core directly. Moreover, it is said this TRIG_OUT may be used to trigger logic analyzer, this assumes the core is running.

Have a great day,
Alexander

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[remyritchen]

Is there a mean to configure Watchpoint monitor block in order to perform a core action, as entering in debug state ?
Is there an other pin than READY_P0 which indicates that core 0 is in debug state?