P2020 DDR3 signals pin delay

[stefanvranken]

Hello,

We are now doing pcb-layout of  P2020 using 4x DDR3 sdram with signals (ck, addr, cmd, control) in fly_by topology  just like on ddr3-udimm.  So we need our P2020 to do ddr3 write leveling to "length-match" our bytelanes with (ck, addr, cmd, control).

Signals (address, command, control) must be length-matched  ± 0.508 mm to ck per dram-chip.

To do this we also need to consider length of P2020-chip bond-wires to its bga balls. E.g. MA10 and MRAS are ~5mm apart on P2020 package.

Is there a (excel) list of bondwire lengths of P2020 ddr3 signals ? Does there exist an orcad symbol of P2020 with DDR3-pin-delays included ?

Kind regards,

Stefan

[r8070z · Accepted solution]

Have a great day,

There is not any public document with list of bondwire lengths of  the P2020 ddr3 signals. It is not needed for the lengths matching. All AC timing parameters related to ddr3 signals are designed and go through rigorous verification process at the P2020 solder ball (i.e. silicon pin). You can match trace lengths starting from the P2020 solder balls.

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