Hello,
During debug, I found that I should add a 4us delay between two times of write data to SPI. If delete this delay,
will cause some of data to be lost.
My code please refer to attached.
sysSpiDrvInitFPGA: is used to initiate SPI controller;
sysSpiWriteDataFPGA: is used to send data to SPI;
In my mind, I only need to check SPIE_DON bit of SPIE register between two times of transmit, not need to
add a delay. But from test, I should add a delay, only check SPIE_DON bit of SPIE register is not enough.
Why?
Could you please help to give some suggestions?
Thank you,
Carl
Original Attachment has been moved to: sysFslSpi.c.zip
Clear the SPIE_DON bit after reading. This bit is not cleared after reading.
Clear SPIE bits by writing a 1-writing 0 has no effect. See the Section 18.3.2 of the P1021 Reference Manual.
Have a great day,
Pavel Chubakov
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Hello Pavel,
Thanks a lot for!
But after I write SPIE_DON to SPIE register to clear the SPIE_DON, still need to add delay, otherwise, will lost some data,
Could you please help to give some further suggestions?
Thank you,
Carl
Look at simple program example for eSPI. Compare this example and your code.
Have a great day,
Pavel Chubakov
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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