P1012: GPIO: What is the relationship between PA0 and CE_PA0?

[carlpeng]

Hello,

What is the relationship bwteen PA0 and CE_PA0 in the p1012RM.pdf?

From the below figure, it seems that PA0 and CE_PA0 indicate the same pin?

But from the signal overview charpter, it seems that for p1012, all GPIO pins are on the QUICC Engine?

Could you please help to clarify it?

Thank you,

Carl

[alexander_yakov]

Yes, CE_PA0 is Quicc Engine pin PA0.

This pin is exposed on LAD8, this is controller by PMUXCR[QE1].

When PMUXCR[QE1] is set to "1" than this pins acts as QE pin PA0 and its function is furter configured in QE registers, as shown in Table 3-7.

Yes, GPIO function is a part of QE, this is correct.

Registers CPPAR, CPDIR, shown in Table 3-7, are described as "GUTS_CPPAR" and "GUTS_CPDIR" in Chapter 20 of P1021 Reference Manual.

Have a great day,
Alexander

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