P1011 eTSEC1 CRC and FCS Errors External PHY

[christianfreita]

Hi,

we use a custom board with the P1011, the linux kernel 3.18 and the gianfar driver version 1.3.

The eTSEC1 module is connected to an external PHY (Broadcom 5461) and the connection type is rgmii-id.

	mdio@24000 {
	phy0: ethernet-phy@10 {
	compatible = "broadcom-5461";
	reg = <0x10>;
	};

	enet0: ethernet@b0000 {
	phy-connection-type = "rgmii-id";
	};

The MDIO connection to the external PHY shows with mii-diag tool no errors and is working fine.

If we send a ping from a host to the board:

- we receive no packet

- we receive ARP request frames with CRC and FCS error (ethtool -S eth0)

- we receive ARP request frame without errors, the kernel responds (tcpdump -vvv) but the host (wireshark) does not receive the response

- if the kernel responds to the ARP requests from the host the TX-LED of the PHY is blinking

Is there a problem between with the GMII module and the PHY?

Is there an handshaking between GMII and PHY?

How can I fix this issue?

[christianfreita]

I could fix this issue by set

- bit 8 register address 18h, shadow value 111b

- bit 9 register address 1Ch, shadow value 11b

of the phy for the RGMII-ID timing in the driver init function.

The generic linux phy driver resets the phy during the linux boot phase.

After this reset, the phy has to be initialized with mentioned RGMII-ID timing settings.

[ufedor]

Please check the following:

1) Ensure that Data to Clock integrated delay is enabled at the PHY side.

2) Use a high-speed digital scope and check that requirements of the P1011 QorIQ Integrated Processor Hardware Specifications, 2.11.3.2 RGMII AC Timing Specifications are fulfilled.

[christianfreita]

The interface works fine with uboot.

It seems that the mii Interface is not configured to RGMII mode.

Which registers should I check for correct RGMII settings in linux?

I checked the eTSEC Interface configuration in function gfar_start_xmit:

GMIIM = 1

TBIM = 0

RPM = 1

R100M = 0

RMM = 0

SGMIIM = 0

I/F = 10

[ufedor]

Provided eTSEC interface configuration is correct - refer to the P1020 QorIQ Integrated Processor Reference Manual, 15.5.8 Ethernet control register (eTSECx_ECNTRL).

[christianfreita]

If we use the Linux Kernel 2.6 we have no problems with eTSEC1. The problems have come with the step 2.6 to 3.18.

The RGMII AC Timing Specifications should be okay.

If debug for fsp_pg_mdio.c is enabled, i see continuously reads from the PHY. Is that okay?

If i measure signals lines of eTSEC1, i see the clock but no the data for sending a ping from P1011 to the host.

The mii-diag tool shows the request and the driver gianfar.c gets the TX Interrupt and counts the sending bytes.

How can I debug the DMA Transfer?

[ufedor]

Which Freescale SDK is used?

[christianfreita]

We use buildroot and not the Freescale SDK.

[ufedor]

Please select a Freescale SDK which already contains all needed customizations.

The latest SDK 1.7 (kernel 3.12) is available at:

Linux® SDK for QorIQ Processors v1.7|Freescale

[scottwood]

Ethernet on P1011 should work with upstream kernels without any SDK "customizations".

If it worked with an older kernel, you could try bisecting.  You could also compare register values under the two kernels and see if any differences look significant.

Another option is to try the latest upstream kernel and ask on relevant upstream mailing lists (linuxppc-dev@lists.ozlabs.org and netdev@vger.kernel.org) with Claudiu Manoil <claudiu.manoil@freescale.com> on CC.